Total dose radiation hard 0.35 /spl mu/m SOI CMOS technology

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a TiSi 2 Schottky gate and display good depletion mode characteristics with a threshold voltage of 0 5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The transistors have been irradiated with 50 keV X-rays to a total ionizing dose in excess of 1 Mrad(Si). After irradiation the threshold voltage of both the top Schottky gate and the back MOS gate shift to more negative values. The shift in threshold is attributed to radiation induced fixed oxide charge at the interface between the SOI channel and the buried oxide.Index Terms-MESFETs, silicon-on-insulator technology, X-ray effects.

“…Our values for also agree well with other published data on the amount of trapped oxide charge which range from to the high [9], [11], [12], [13].…”

Section: Radiation Test and Measurementsupporting

confidence: 93%

Section: Radiation Test and Measurementmentioning

confidence: 88%

Total dose radiation response of CMOS compatible SOI MESFETs

Spann

Kushner

Thornton

et al. 2005

“…Both nFETs and pFETs have lightly doped drain (LDD) structures to improve hot electron reliability. The body tie is formed by a connection at each end of the gate [16], [17].…”

Section: Methodsmentioning

confidence: 99%

Probing proton damage in SOI CMOS technology by using lateral bipolar action

Niu

Cressler³

et al. 2003

We investigate proton damage in SOI CMOS devices on UNIBOND using a variety of lateral bipolar operational modes. We show that the impact of interface states and oxide charge can be more clearly observed using lateral bipolar action than by using normal FET operational characteristics. We also investigate the radiation-induced interface states at the Si/buried oxide interface and oxide charges in the buried oxide of this SOI CMOS technology using the DCIV method.

“…The test devices and micropower preamplifier considered here were fabricated in Honeywell's 0.35-m partially-depleted SOI CMOS process [29]. The starting substrate was a UNI-BOND SOI material that was developed using a thermal oxide and Smart-Cut process to adjust oxide thickness.…”

Section: 35-m Pd Soi Cmos Processmentioning

confidence: 99%

Noise performance of 0.35-/spl mu/m SOI CMOS devices and micropower preamplifier following 63-MeV, 1-mrad (Si) proton irradiation

Binkley

Hopper

Cressler

et al. 2004

Total dose and single-event radiation hardness, and operation over extreme temperatures make silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) processes leading contenders for space applications. This paper reports noise degradation of 0.35-m partially-depleted SOI CMOS devices and a micropower, low-noise preamplifier following 63-MeV proton irradiation to 1 Mrad (Si). Proton irradiation, relevant for space mission environments, was considered since it induces both ionizing and displacement damage. Preamplifier input-referred white-noise voltage was minimized at low power consumption by operating input devices in moderate inversion for high transconductance efficiency. Flicker-noise, important for gyros and other mission sensors having low-frequency outputs, was minimized by large-area pMOS input devices and careful management of noninput devices. Measured 1-Hz gate-referred, flicker-noise voltage density increased 24 and 32% for pMOS and nMOS test devices respectively following 1 Mrad (Si) irradiation. Measured 1-Hz input-referred noise voltage density increased 22% between a nonirradiated and radiated preamplifier sample, which agrees closely with the 24% increase expected since noise is dominated by pMOS input devices. Device small-signal transconductance and white-noise were largely unchanged while output conductance appeared to increase over a factor-of-three. This suggests a modest design margin is required to maintain flicker noise performance, while substantial design margin may be required to maintain open-loop voltage gain.Index Terms-Analog complementary metal oxide semiconductor (CMOS), flicker noise, micropower, moderate inversion, noise, output conductance, preamplifier, proton irradiation, radiation effects, silicon-on-insulator (SOI), space applications, transconductance efficiency.