Total-Dose Failure Mechanisms of Integrated Circuits in Laboratory and Space Environments

Abstract

Total-dose failure mechanisms are identif ied over a wide range of dose rate for 2K and 16K SRAMs from hardened and commercial CMOS technologies. Failure was defined "parametrically," such that an IC fails if one of its parameters, e.g., static power supply current or timing, exceeds a preset specification following irradiation. These studies demonstrate that the dominant failure mechanisms of SRAMs in space radiation environments are often quite different than those observed at considerably higher laboratory dose rates specified by DoD test guidelines, i.e., 100 to 300 rad(Si)/s. In addition, the total-dose hardness of SRAMs varied significantly between laboratory and space dose rates. Several approaches are discussed for predicting total-dose hardness of ICs in space from laboratory measurements. Results are also presented for transistors irradiated over the same range of dose rate (200 to 0.02 rad(Si)/s) and at all biases, i.e., N-on/off and P-on/off. These transistor measurements are used to characterize the physical mechanisms that govern the radiation response of the more complex SRAMs. In a surprising result, a dose-rate dependence for the buildup of radiation-induced interface states was observed.At dose rates from 200 to 0.02 rad(Si)/s, the number of interface states at a given total dose increased as the dose rate decreased.

Effects of device aging on microelectronics radiation response and reliability

“…Threshold voltage shifts due to interface traps as a function of radiation dose rate for 3 lm · 16 lm transistors with radiation-hardened 45 nm oxides that were fabricated, packaged, and tested at Sandia National Laboratories in 1987. Interface-trap buildup with 0 V gate bias is observed to be strongly enhanced at low dose rates, consistent with enhanced low-dose-rate sensitivity and/or potential aging effects in these devices (after [17]). Ó IEEE, used with permission 1987 SiO 2 (in the absence of defects or impurities that can serve as cracking sites [15]), and are available to contribute to the passivation of dangling bonds at the Si-SiO 2 interface.…”

“…10 and 11 may lead to significant complications in evaluations of dose-rate and temperature effects in MOS and linear bipolar devices. As one potential past example, Winokur et al reported a larger increase in the enhancement of interface-trap buildup at low dose rates in [17] for MOS transistors from different processing and packaging lots than in follow-on work reported in [13]. The enhancement in interface-trap density was especially large at zero bias (Fig.…”

“…12). While factors related to dosimetry were identified in [13] that may account for some of the differences in results between [13] and [17], the work reported in [12] suggests that differences in aging responses of the two different types of devices in [13] and [17] (processed differently, and packaged at different times, relative to their respective irradiation and annealing tests) may also have contributed to the observed differences in apparent doserate dependence of interface-trap buildup. Thus, it can be difficult to distinguish true or apparent dose rate effects from changes in device radiation response due to aging effects during a low-dose-rate radiation exposure.…”

Magnetic Random Access Memory for Embedded Computing

“…Fixed interface states may accumulate at the surface, resulting in a decrease in carrier mobility through the channel and a positive shift in transistor thresholds [58]. A number of factors have been identified that influence the magnitude of total dose effects that any particular integrated circuit will exhibit, including seemingly unrelated issues such as plastic packaging and burn-in [57].…”

Thermal-stress effects and enhanced low dose rate sensitivity in linear bipolar ICs

“…We now consider whether the differences in IB+ at high total doses in Figure 6 are (1) a true dose rate effect, (2) a simple time-dependent effect, due to the longer times associated with the low-doserate irradiation, or (3) a combination of both types of effects. To address this question, the devices irradiated at 50 rad(Si02)/s were annealed at room temperature with all pins grounded for times up to 106s (which is an equivrdent time to 100 krad(SiOJ irradiation at 0.1 rad(SiOJ/s) [20], [21]. The results are shown in Figure 7, where IB+is plotted as a function of irradiation and anneal time for the 0.1 and 50 rad(SiOz)/s irradiations for LM1 11s subjected to a 175"C, 100-hour stress.…”