Topology-induced Enhancement of Mappings

Abstract

In this paper we propose a new method to enhance a mapping µ(·) of a parallel application's computational tasks to the processing elements (PEs) of a parallel computer. The idea behind our method TIMER is to enhance such a mapping by drawing on the observation that many topologies take the form of a partial cube. This class of graphs includes all rectangular and cubic meshes, any such torus with even extensions in each dimension, all hypercubes, and all trees.Following previous work, we represent the parallel application and the parallel computer by graphs G a = (V a , E a ) and G p = (V p , E p ). G p being a partial cube allows us to label its vertices, the PEs, by bitvectors such that the cost of exchanging one unit of information between two vertices u p and p of G p amounts to the Hamming distance between the labels of u p and p .By transferring these bitvectors from V p to V a via µ −1 (·) and extending them to be unique on V a , we can enhance µ(·) by swapping labels of V a in a new way. Pairs of swapped labels are local w. r. t. the PEs, but not w. r. t. G a . Moreover, permutations of the bitvectors' entries give rise to a plethora of hierarchies on the PEs. Through these hierarchies we turn TIMER into a hierarchical method for improving µ(·) that is complementary to state-of-the-art methods for computing µ(·) in the first place.In our experiments we use TIMER to enhance mappings of complex networks onto rectangular meshes and tori with 256 and 512 nodes, as well as hypercubes with 256 nodes. It turns out that common quality measures of mappings derived from state-of-the-art algorithms can be improved considerably.

Recursive Multi-Section on the Fly: Shared-Memory Streaming Algorithms for Hierarchical Graph Partitioning and Process Mapping

“…To reduce the runtime, Brandfass et al [9] introduced a couple of modifications to speed up this local search, such as only considering pairs of PEs that can reduce the objective or partitioning the search space into some consecutive blocks and only performing swaps inside those blocks. Glantz et al [16] proposed a one-to-one mapping algorithm in which the hardware topology is an isometric subgraph of a hypercube and labeled the nodes and the PEs with bit-strings in order to optimize the algorithm locality. Schulz and Träff [36], proposed a top-down multi-section approach to map blocks to PEs when the communication topology is a regular hierarchy.…”

More Recent Advances in (Hyper)Graph Partitioning

“…Glantz et al [75] propose a local improvement algorithm for one-to-one process mapping in which the hardware topology is a partial cube, i.e., an isometric subgraph of a hypercube. The authors exploit the regularity of these topologies to label PEs as well as processes with bit-strings along convex cuts.…”

Load-Balanced Bottleneck Objectives in Process Mapping

“…[1]. Later, based on a variety of techniques, more sophisticated algorithms to compute mappings for hierarchical systems have been published [27,10,8].…”