Topology comparison and design optimisation of the buck converter and the single-inductor dual-output converter for system-in-package in 65nm CMOS

Abstract

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A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration

“…1. In [19], a high-level optimization procedure is presented that compares the maximum attainable efficiency for such an integrated DC-DC converter when using an air-core inductor or a thin-film magnetic-core inductor based on NiFe magnetic material as presented in [20]. Using such a thin-film magnetic-core inductor results in higher efficiency at the cost of higher passive silicon area [19].…”

“…In [19], a high-level optimization procedure is presented that compares the maximum attainable efficiency for such an integrated DC-DC converter when using an air-core inductor or a thin-film magnetic-core inductor based on NiFe magnetic material as presented in [20]. Using such a thin-film magnetic-core inductor results in higher efficiency at the cost of higher passive silicon area [19]. The efficiency of this type of inductor is close to that obtained with commercial low-value chip inductors [20], so in case the footprint can be decreased sufficiently, this would be an attractive option for future integrated DC-DC converters.…”

“…For example, overlap losses (simultaneous non-zero current through and voltage across power switches when switching on or off) and body-diode conduction losses have not been included. Moreover, the impact of voltage drop across the power switches and inductor on the actual duty-cycle value as taken into account in [19] has also been neglected. However, as will be shown in section IV, the eventual measurement results, where all effects not taken into account occur, are rather close to the results predicted by the design-space exploration.…”

Survey of modelling techniques used in optimisation of power electronic components

“…In [77], transformer current waveform is considered to be sinusoidal (and confirmed by measurement), and therefore an equivalent resistance for sinusoidal waveform is used. In [84], an equivalent resistance is used to model both core losses and copper losses, and the resistance is calculated from curve fitting. In [29, 41, 52, 67–69, 71, 74, 75, 85, 86], equivalent resistance is used; however, no reason is specified for neglecting high‐frequency effects.…”

“…MOSFET conduction losses are usually calculated using a simple on state equivalent resistance [23, 24, 27, 29, 33–38, 44, 46, 50, 52, 67, 71, 75, 77, 84–86, 90–92]. In most of the papers, this resistance ( R ds,ON ) is obtained from the MOSFET datasheet and multiplied by RMS current square to calculate conduction losses [23, 24, 29, 33–36, 38, 44, 46, 50, 52, 67, 71, 75, 77, 84, 85, 93, 94]. Some of the other papers attempt to calculate or scale R ds,ON based on some device‐level characteristics or operational characteristics of the MOSFET.…”