State-of-the-Art of Integrated Switching Power Converters

Piqué, Gerard Villar; Bergveld, Henk Jan

doi:10.1007/978-94-007-1926-2_13

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Power Delivery Architecture1

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2021

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Cited by 8 publications

(1 citation statement)

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“…CoreUnfolding off-chip: In the case of an off-chip VR, CoreUnfolding enables the VR to benefit from a lower step-down ratio [Piqué and Bergveld 2012]. This is shown in Figure 8(c).…”

Section: Power Delivery Architecturementioning

confidence: 99%

Managing Mismatches in Voltage Stacking with CoreUnfolding

Ardestani

Possignolo

Briz

et al. 2015

ACM Trans. Archit. Code Optim.

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Five percent to 25% of power could be wasted before it is delivered to the computational resources on a die, due to inefficiencies of voltage regulators and resistive loss. The power delivery could benefit if, at the same power, the delivered voltage increases and the current decreases. This article presents CoreUnfolding, a technique that leverages voltage Stacking to improve power delivery efficiency. Our experiments show that about 10% system-wide power can be saved, the voltage regulator area can be reduced by 30%, di/dt improves 49%, and the power pin count is reduced by 40% (≈20% reduction in packaging costs), with negligible performance degradation.

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“…CoreUnfolding off-chip: In the case of an off-chip VR, CoreUnfolding enables the VR to benefit from a lower step-down ratio [Piqué and Bergveld 2012]. This is shown in Figure 8(c).…”

Section: Power Delivery Architecturementioning

confidence: 99%