Tools for the computer-aided design of multigigahertz superconducting digital circuits

Gaj, Kris; Herr, Q.P.; Adler, V.; Krasniewski, Andrzej; Friedman, Eby G.; Feldman, M.J.

doi:10.1109/77.763251

Cited by 75 publications

(18 citation statements)

References 47 publications

(70 reference statements)

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“…For complex SFQ systems, the automated routing process determines the topology and method to connect cells while satisfying design constraints. These methods are intended as guidelines for EDA tools to enable robust routing with superconductive interconnects [3,45,46]. Routing in SFQ systems is preferably performed with one of two approaches, based on whether the path is local or global.…”

Section: Automated Routing In Sfq Systemsmentioning

confidence: 99%

Global interconnects in VLSI complexity single flux quantum systems

Jabbari

Friedman

2020

Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop

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Section: Automated Routing In Sfq Systemsmentioning

confidence: 99%

Global interconnects in VLSI complexity single flux quantum systems

Jabbari

Friedman

2020

Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop

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“…Though design automation of RSFQ circuits has been studied [6], [7], designing an RSFQ logic circuit is still a burdensome task. In this paper, we propose a method for converting a CMOS logic circuit design to an efficient RSFQ circuit design.…”

Section: Introductionmentioning

confidence: 99%

Conversion of a CMOS logic circuit design to an RSFQ design considering latching function of RSFQ logic gates

Kito

Takagi

2014

IEEE Trans. Appl. Supercond.

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A method for converting a CMOS logic circuit design to an efficient RSFQ design, which minimizes the number of flip-flops during conversion, is proposed. In an RSFQ circuit, each data input terminal of a logic gate has latching function, and the function is enabled or disabled depending on the order of the arrivals of the data pulse and the corresponding clock pulse. The number of flip-flops is minimized by the use of the latching functions through arrangement of the order of pulse arrivals of each gate and also by circuit retiming. A conversion tool based on the proposed method has been developed. Conversion results of CMOS benchmark circuits show that most of the flip-flops in the circuits are eliminated by the proposed method. A 4-bit RSFQ processor was successfully designed by an existing CMOS design tool and the developed conversion tool.

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“…Because of unique properties of the SFQ circuits compared with semiconductor digital circuits, the development of new design methodologies, which are suitable for the SFQ circuits and bring out their ultimate ability, is desirable [2].…”

Section: Introductionmentioning

confidence: 99%

Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

Yoshikawa

Yoda

Hoshina

et al. 2003

IEEE Trans. Appl. Supercond.

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We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and don't need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. In the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.Index Terms-Binary decision diagram, cell base design, cell library, RSFQ, superconducting circuits.

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Tools for the computer-aided design of multigigahertz superconducting digital circuits

Cited by 75 publications

References 47 publications

Global interconnects in VLSI complexity single flux quantum systems

Global interconnects in VLSI complexity single flux quantum systems

Conversion of a CMOS logic circuit design to an RSFQ design considering latching function of RSFQ logic gates

Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

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