Tools for correct DSP synchronization

The RELICS language is a systolic programming language, which simplifies the programmer's task by making explicit the data-flow of systolic algorithms, and by exposing the data delivery mechanism. The underlying architecture model is different from other SIMD architectures in that it physically separates computation and data management. We introduce the RELICS language as a syntaxic and a semantic extension of the C language. We show that the RELICS programming model provides a simple programming method for systolic algorithms, which is applicable to a variety of parallel machines.

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RELACS for systolic programming

Raimbault

Lavenier

Proceedings of International Conference on Application Specific Array Processors (ASAP '93)

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From behavioral to RTL models: an approach

Lavenier¹,

McConnell²

Proceedings of IEEE 5th International Workshop on Rapid System Prototyping

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VSDF: synchronous data flow for VLSI

Kerihuel

McConnell

Rajopadhye

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems

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Tools for correct DSP synchronization

Cited by 3 publications

References 3 publications

RELACS for systolic programming

RELACS for systolic programming

From behavioral to RTL models: an approach

VSDF: synchronous data flow for VLSI

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