VSDF: synchronous data flow for VLSI

Kerihuel, A.; McConnell, R.; Rajopadhye, Sanjay

doi:10.1109/mwscas.1994.519263

Cited by 4 publications

(4 citation statements)

References 8 publications

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“…The application is modeled using VSDF (Synchronous Data Flow for VLSI) semantics [6]. The application model is illustrated in Figure 4, where actor bm computes and normalizes the branch metric; actor b acs chooses the survivor path; and actor reg ex stores the outcome.…”

Section: Methodsmentioning

confidence: 99%

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Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays

Shen

Bhattacharyya

et al. 2010

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers

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Section: Methodsmentioning

confidence: 99%

“…For example, the size of the switch that connects the four PEs located at (1, 6), (1,7), (2,6), and (2, 7) is defined by X channel [6] and Y channel [1], and the total number of switches in the FPXA is…”

Section: Fpxa Architecturementioning

confidence: 99%

Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays

Shen

Bhattacharyya

et al. 2010

2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers

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“…12 The VSDF model eases the transition between a synchronous dataflow and an implementation using specialized VLSI synchronous circuits. It introduces a time-aware notation that allows to specify a model and statically verify correct synchronization at Register-transfer Level.…”

Section: Related Workmentioning

confidence: 99%

Time-triggered static schedulable dataflows for multimedia systems

Arumí

Amatriain

2009

SPIE Proceedings

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Software-based reactive multimedia computation systems are pervasive today in desktops but also in mobile and ultra-portable devices. Most such systems offer a callback-based architecture to incorporate specific stream processing. The Synchronous Dataflow model (SDF) and its variants are appropriate for many continuous stream processing problems such as the ones involving video and audio. SDF allows for static scheduling of multi-rate processing graphs therefore enabling optimal run-time efficiency. But the SDF abstraction does not adapt well to real-time processing because it lacks the notion of time: executing non-trivial schedules of multi-rate dataflows in a time-triggered callback architecture, though possible through buffering, causes jitter, excessive latency and run-time inefficiencies. In this paper we formally describe a new Time-Triggered SDF (TTSDF) model with a static scheduling algorithm that produces periodic schedules than can be split among several callback activations, solving the above-mentioned problems. The model has the same expressiveness than SDF, in the sense that any graph computable by one model will also be computable by the other. Additionally, it enables parallelization and run time load balancing between callback activations.

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“…The VSDF [13] and multirate hierarchical timing pair (MHTP) [7] models are dataflow modeling techniques that are geared towards efficient hardware implementation.…”

Section: Motivation and Related Workmentioning

confidence: 99%

Consistency Analysis of Reconfigurable Dataflow Specifications

Bhattacharya

Bhattacharyya

2002

Embedded Processor Design Challenges

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Abstract. Parameterized dataflow is a meta-modeling approach for incorporating dynamic reconfiguration capabilities into broad classes of dataflow-based design frameworks for digital signal processing (DSP). Through a novel formalization of dataflow parameterization, and a disciplined approach to specifying parameter reconfiguration, the parameterized dataflow framework provides for automated synthesis of robust and efficient embedded software. Central to these synthesis objectives is the formulation and analysis of consistency in parameterized dataflow specifications. Consistency analysis of reconfigurable specifications is particularly challenging due to their inherently dynamic behavior. This paper presents a novel framework, based on a concept of local synchrony, for managing consistency when synthesizing implementations from dynamicallyreconfigurable, parameterized dataflow graphs. Motivation and related workDataflow is an established computational model for simulation and synthesis of software for digital signal processing (DSP) applications. The modern trend toward highly dynamic and reconfigurable DSP system behavior, however, poses an important challenge for dataflow-based DSP modeling techniques, which have traditionally been well-suited primarily for applications with significantly static, high-level structure. Parameterized dataflow [1] is a promising new meta-modeling approach that addresses this challenge by systematically incorporating dynamic reconfiguration capabilities into broad classes of dataflow-based design frameworks for digital signal processing (DSP).Through a novel formalization of dataflow parameterization, and a disciplined approach to specifying parameter reconfiguration, the parameterized dataflow framework provides for automated synthesis of robust and efficient embedded software.

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VSDF: synchronous data flow for VLSI

Cited by 4 publications

References 8 publications

Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays

Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays

Time-triggered static schedulable dataflows for multimedia systems

Consistency Analysis of Reconfigurable Dataflow Specifications

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