Tools and techniques for converting simulation models into test patterns

Taylor, T.A.

doi:10.1109/test.1993.470709

Cited by 4 publications

(1 citation statement)

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“…Implementing at-speed functional test using simulation waveforms has been proposed to recreate the customers' environment on automatic test equipment (ATE) [17,18]. However, high-functionality ICs having asynchronous clock domains require expensive ATE that can provide multiple asynchronous clocks during test.…”

Section: Introductionmentioning

confidence: 99%

At-Speed Structural Test For High-Performance ASICs

Iyengar

Yokota²,

Yamada³

et al. 2006

2006 IEEE International Test Conference

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At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-offscan clocking without the need to switch a scan enable atspeed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

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Section: Introductionmentioning

confidence: 99%