A flexible and scalable methodology for GHz-speed structural test

Iyengar, V.; Grise, G.; Taylor, Mark

doi:10.1145/1146909.1146992

Cited by 4 publications

(3 citation statements)

References 13 publications

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“…Many solutions for scan-based at-speed testing have been introduced and are gaining industry acceptance recently [2], [8]. The basic idea is to generate at-speed test clock pulses on-chip for the launch and capture events, while the other shift cycles are pulsed at lower speed to control the test power.…”

Section: A Multifrequency At-speed Testingmentioning

confidence: 99%

“…To apply this, the bottleneck VC is first transformed to a temporary VC which operates at F M (line 4). Inside the inner loop (lines [8][9][10][11][12][13][14][15][16][17][18][19], the algorithm selects the shift frequency that minimize the cost and at the same time satisfies the power constraint (lines 12,15). The cost function is built as in line 11, in which normalWeight is a constant used to match the TAT and the power consumption into comparable values.…”

Section: B Heuristic For Wrapper Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Nicolici

Chakrabarty

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Even though many embedded cores contain several clock domains, most published methods for wrapper design have been limited to single-frequency cores. Cumbersome and invasive design techniques, such as insertion of test points, are needed to make these methods applicable to current-generation embedded cores. This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. The proposed 1500-compliant wrapper prevents clock skew and allows scan chains in different clock domains to shift test data at distinct clock frequencies, which enables a better control of power dissipation during test. We present an integer linear programming (ILP) model that can be used to minimize the core testing time under power constraints for small problem instances, and which can be combined with LP-relaxation to obtain lower bounds on the testing time for larger instances. We also present an efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances.

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Section: A Multifrequency At-speed Testingmentioning

confidence: 99%

Section: B Heuristic For Wrapper Optimizationmentioning

confidence: 99%

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Nicolici

Chakrabarty

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In [13], a programmable Test Waveform Generator (TWG) driven by on-chip PLL is proposed to improve the flexibility of generating capture clock sequences. For each functional clock, a TWG including 2 shift-registers is used to create the desired clock waveforms.…”

Section: Introductionmentioning

confidence: 99%

Programmable Logic BIST for At-speed Test

Huang¹,

Xiao²

2007

16th Asian Test Symposium (ATS 2007)

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In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the maximum number of applied BIST test patterns is specified. Experimental results show the effectiveness of the proposed method on achieving higher test coverage than the method with test patterns evenly distributed among different test sessions. 16th IEEE Asian Test Symposium

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Test Strategies for Gated Clock Designs

Keller

Chakravadhanula

2009

Power-Aware Testing and Test Strategies for Low Power Devices

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A flexible and scalable methodology for GHz-speed structural test

Cited by 4 publications

References 13 publications

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Programmable Logic BIST for At-speed Test

Test Strategies for Gated Clock Designs

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