Programmable Logic BIST for At-speed Test

Abstract

In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the maximum number of applied BIST test patterns is specified. Experimental results show the effectiveness of the proposed method on achieving higher test coverage than the method with test patterns evenly distributed among different test sessions. 16th IEEE Asian Test Symposium

An on-Chip Clock Controller for Testing Fault in System on Chip

“…When doing test pattern generation for the delay defects, the types of fault models, such as the transition fault model, have been used extensively in industry [11]. To test the transition-delay faults used the fast clock, the PLL logic which can output the clock multiplier in the SOC must be used.…”