2018 IEEE International Electron Devices Meeting (IEDM) 2018
DOI: 10.1109/iedm.2018.8614594
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Too Noisy at the Bottom? —Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits

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Cited by 25 publications
(37 citation statements)
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“…Our result also shows that ΔID/ID0 are larger around threshold region and reduce towards the operating region. This agrees well with the 3D atomic simulation results by assuming different distances between individual traps in the dielectric and the percolation path in the channel induced by the non-uniform doping [23]. Since the standard RTN test measures ΔID/ID0 close to threshold region, this result suggests that the time-dependent variation could be overestimated [24].…”
Section: Applications To Rtn Study In Nano-scaled Devicesupporting
confidence: 86%
“…Our result also shows that ΔID/ID0 are larger around threshold region and reduce towards the operating region. This agrees well with the 3D atomic simulation results by assuming different distances between individual traps in the dielectric and the percolation path in the channel induced by the non-uniform doping [23]. Since the standard RTN test measures ΔID/ID0 close to threshold region, this result suggests that the time-dependent variation could be overestimated [24].…”
Section: Applications To Rtn Study In Nano-scaled Devicesupporting
confidence: 86%
“…To take RTN into account when optimizing circuit design, substantial efforts have been made to model RTN [6]- [11]. For dynamic Monte Carlo modelling, one needs the statistical distributions of the number of traps per device, the amplitude of RTN per trap, and the capture/emission time (CET) of traps [3], [11], [12]. Early works [9], [13] have focused their attentions on the amplitude distributions and the CET distribution has been rarely reported based on test data [1], [14]- [17].…”
Section: Introductionmentioning
confidence: 99%
“…Although this raises the number of traps analyzable from one device, it becomes increasingly difficult to apply as the number of traps in a device increases with time window. Although it is generally believed that there is no clear uplimit for CETs [1], [3], [12], [21], the time window used in early works is often limited, e.g. 10 sec or less [14], [17], partially to control the number of active traps and partially for test convenience.…”
Section: Introductionmentioning
confidence: 99%
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“…The instabilities of modern MOSFETs have a number of sources: bias temperature instabilities (BTI) [1][2][3][4][5][6][7], hot carrier ageing (HCA) [8][9][10], and random telegraph noise [11][12][13][14][15][16][17]. To increase the instabilities and make them measurable, it is a common practice to use voltage-acceleration [1][2][3][4][5][6][7][8][9][10].…”
Section: Introductionmentioning
confidence: 99%