TLM2.0 based timing accurate modeling method for complex NoC systems

Abstract

Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC.The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and verification of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method.

Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol

“…Transaction level modeling (TLM) [3][4][5][6][7] is a core technique for ESL design and verification. In TLM, generic payloads (transaction classes) are used in the communication between modules.…”