2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) 2018
DOI: 10.1109/ipdpsw.2018.00028
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TiReX: Tiled Regular eXpression Matching Architecture

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Cited by 12 publications
(11 citation statements)
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References 17 publications
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“…We move then to Neorv32 [33], a VHDL-based RISC-V core, where we apply the power of two restrictions to explore core memories space. Finally, we explore a VHDL-based Architecture called TiReX [34] where we explore both the datapath and memories parameter spaces.…”
Section: Experimental Setup and Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…We move then to Neorv32 [33], a VHDL-based RISC-V core, where we apply the power of two restrictions to explore core memories space. Finally, we explore a VHDL-based Architecture called TiReX [34] where we explore both the datapath and memories parameter spaces.…”
Section: Experimental Setup and Resultsmentioning
confidence: 99%
“…TiReX [34] is a domain-specific architecture tailored for the Regular Expressions domain. We explore the architecture scaling according to datapath and memories parameters, targeting a Zynq Ultrascale+ XCZU3EG and the same Kintex-7 for the implementation phase.…”
Section: Tirex: Vhdl Dsa For Regular Expressionsmentioning
confidence: 99%
“…They encode the DFA as a set of rules into the memory of a softwareprogrammable DFA engine by exploiting the B-FSM concept for reprogrammable DFA [34]. Comodi et al [8] present an architecture that exploits a VLIW-like approach for a DFA with backtracking execution mode. All these methods are based on the DFA representation, which grows exponentially with the complexity of the RE.…”
Section: Related Workmentioning
confidence: 99%
“…RE matching is an essential kernel [2] for traditional computer security [32,41] and database queries [19,31] but also for novel domains such as natural language processing [35,42], and genomeprotein matching [8,36]. The literature contains different algorithms to tackle RE matching.…”
Section: Introductionmentioning
confidence: 99%
“…Alessandro Comodi et al, (IEEE 2018) [1], proposes a novel and efficient RE matching architecture for FPGAs, based on the concept of matching core. RE can be software-compiled into sequences of basic matching instructions that a matching core runs on input data, and can be replaced to change the RE to be matched.…”
Section: Review Of Literaturementioning
confidence: 99%