Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques

Savugathali, Salahuddin; Mustapa, Muslim; Razali, Mohammed Sharazel; Zakaria, Fazrul Faiz

doi:10.11591/ijeecs.v14.i2.pp628-636

Cited by 2 publications

(2 citation statements)

References 10 publications

(12 reference statements)

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“…Timing exceptions block consists of clock information and exceptions of soft IP in SDC format. In general, constraints are present for functional synthesis and timing [13]. Similarly, timing constraints for the DFT part must be taken care of to proceed further in the digital flow.…”

Section: Design Setup To Generate the Dft Timing Constraintsmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints.

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Section: Design Setup To Generate the Dft Timing Constraintsmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

View full text Add to dashboard Cite

show abstract

“…An FPGA implementation of efficient image encryption algorithm using a chaotic map has been proposed proposed by [11]. The Failed Path Fixes technique proposed by [12] to reduce the timing violation in the FPGA prototyped design. Ooe [13] proposed a system uses an FPGA home hub as its local analytic engine with an IoT platform to store the sensory data.…”

Section: Introductionmentioning

confidence: 99%

DES encryption and decryption algorithm implementation based on FPGA

Zeebaree

2020

IJEECS

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Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept. The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

show abstract

Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques

Cited by 2 publications

References 10 publications

An effective way to generate the shift timing constraints and sanity checks

An effective way to generate the shift timing constraints and sanity checks

DES encryption and decryption algorithm implementation based on FPGA

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