Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

Rebaud, Bettina; Belleville, Marc; Beigné, Edith; Bernard, Christian; Robert, Michel; Maurine, Philippe; Azémard, Nadine

doi:10.1016/j.mejo.2011.02.005

Cited by 11 publications

(10 citation statements)

References 18 publications

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“…Although the basis of this architecture has been demonstrated in literature [Rebaud et al 2011;Vincent et al 2012;Agkul et al 2012], practical realizations fully exploiting the additional functionalities of emerging devices still need to be explored, thereby opening broad research horizons towards even lower power consumption in complex systems.…”

Section: Perspectives: An Ideal Avfs Architecture Fully Unlocking Emementioning

confidence: 99%

A Survey on Low-Power Techniques with Emerging Technologies

Gaillardon

Beigné

Lesecq

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall-around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.

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Section: Perspectives: An Ideal Avfs Architecture Fully Unlocking Emementioning

confidence: 99%

A Survey on Low-Power Techniques with Emerging Technologies

Gaillardon

Beigné

Lesecq

et al. 2015

J. Emerg. Technol. Comput. Syst.

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“…5. Since these buffers are also needed for the edge detector designs in [13], [24], [26], these extra buffers are excluded for each design during comparison in Table I. Inserting more buffers creates wider edge which is needed for proper functioning of the warning FF.…”

Section: A Edge Detectormentioning

confidence: 99%

“…However, a comparator is needed to monitor the two code words which in turn increase the area of the sensor circuit. The timing slack monitoring circuit with a window generator and a sensor cell is presented in [24]. As large number of buffers are required in the window generator circuit which would lead to difficulty in balanced clock tree synthesis and large clock power consumption.…”

Section: Introductionmentioning

confidence: 99%

Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs

Das

Onodera

2014

IEEE Trans. VLSI Syst.

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In this paper, a metastability immune warning flipflop (FF) is proposed which consists of an edge detector, a warning window generator and a warning detector along with a traditional FF. The delayed data is monitored during the warning window to flag a warning signal before the data enters the erroneous zone. In this scheme, the warning window is independent of input clock frequency and hence is suitable for frequency scaling application. A 16-bit Kogge-stone adder is implemented in 65 nm technology which uses warning FF for dynamic voltage and frequency scaling (DVFS). The warning FF based DVFS allows elimination of safety margins and operates till the point of first warning of the adder without any erroneous results. Experiments were conducted with different supply voltages, phase-shifted clocks and process conditions. The circuit is helpful to determine when to stop further reduction in supply voltage by producing the warning signal with pre-defined timing slacks in DVFS application. The test chip results demonstrate that the proposed circuit can track the critical path delay of 2.4 ns to 7.5 ns at warning voltage of 1.15 V to 0.72 V respectively. The measured results from 10 different chips show effectiveness of the proposed concept across process variation.

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“…Similar works proposed to anticipate timing failures rather than recovering after their occurrence [12]. Another popular approach consists in directly measuring critical path delay using a Time-toDigital Converter (TDC) [9] to translate timing information into digital values.…”

Section: Related Workmentioning

confidence: 99%

“…The need of such dynamic monitoring of performance has spurred a vast amount of literature concerned with the implementation of embedded delay monitors with the most diverse characteristics [5], [8], [10], [12], [15], [17]. All these implementations are useful in different ways depending on the true objective of the measurement.…”

Section: Introductionmentioning

confidence: 99%

A fully standard-cell delay measurement circuit for timing variability detection

Sassone¹,

Petricca²,

Poncino³

et al. 2013

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitive to process, voltage and temperature variations as well as to aging effects, generally resulting into a mismatch between the simulated path delay of the circuit obtained with CAD tools and the actual path delay on the manufactured chip. In order to solve this issue and to also avoid conservative strategies based on increasing time margins, adaptive techniques are the most desirable solution because they should automatically sense and correct timing variations online. Implementing such adaptive strategies requires accurate, high resolution and compact delay measurement devices. In this work we propose an effective, fully-digital, online delay measurement circuit that can be entirely implemented in a standard cell technology without the need of custom elements. Our design provides low-cost multi-paths delay monitoring while achieving high accuracy of the measurements (in the order of 30ps).

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Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

Cited by 11 publications

References 18 publications

A Survey on Low-Power Techniques with Emerging Technologies

A Survey on Low-Power Techniques with Emerging Technologies

Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs

A fully standard-cell delay measurement circuit for timing variability detection

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