Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs

Abstract

In this paper, a metastability immune warning flipflop (FF) is proposed which consists of an edge detector, a warning window generator and a warning detector along with a traditional FF. The delayed data is monitored during the warning window to flag a warning signal before the data enters the erroneous zone. In this scheme, the warning window is independent of input clock frequency and hence is suitable for frequency scaling application. A 16-bit Kogge-stone adder is implemented in 65 nm technology which uses warning FF for dynamic voltage and frequency scaling (DVFS). The warning FF based DVFS allows elimination of safety margins and operates till the point of first warning of the adder without any erroneous results. Experiments were conducted with different supply voltages, phase-shifted clocks and process conditions. The circuit is helpful to determine when to stop further reduction in supply voltage by producing the warning signal with pre-defined timing slacks in DVFS application. The test chip results demonstrate that the proposed circuit can track the critical path delay of 2.4 ns to 7.5 ns at warning voltage of 1.15 V to 0.72 V respectively. The measured results from 10 different chips show effectiveness of the proposed concept across process variation.

Monitor Circuits for Cross-Layer Resiliency

“…In the case of in-situ monitors, the Flip-Flops (FF) in a circuit are replaced with special FFs with error detection sequential (EDS) functions. The EDS can either detect whether a timing error has occurred [8,9] or warn us before the occurrence of actual errors [10][11][12]. Supply voltage and clock frequency are adapted accordingly based on the EDS signals.…”

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

“…TEP circuits [1][2][3][4][5][6] predict a potential error by monitoring data signals. It flags a warning signal whenever the delayed data signals enter an erroneous timing zone that is defined with a clock signal.…”