Timing models in VAL/VHDL

A procedure for software synthesis from VHDL models

“…In particular we concern ourselves with inertial and transport delays, which are supported by the VHDL language. Augustin [5] describes the semantics associated with these delay models. The VHDL Language Reference Manual [6] contains an algorithm to implement the preemptive semantics associated with signal assignments.…”

“…The VHDL Language Reference Manual [6] contains an algorithm to implement the preemptive semantics associated with signal assignments. Augustin [5] and Allen [7] provide formal frameworks within which it is possible to analyze the behavior of the waveforms associated with signals in VHDL. The former provides a waveform algebra within which it is possible to define and manipulate waveforms and their interactions with one another.…”

“…In other words, transactions posted by one assignment statement may be invalidated by another assignment to the same signal. To understand this consider the example of events in Figure 1 from [5]. Transactions that cause events earlier than already scheduled events result in invalidation of existing events.…”

“…VHDL signal assignment has preemptive semantics [5]. As soon as a transaction is posted by the execution of the signal assignment statement, other transactions on the transaction list are examined for possible preemption as follows.…”

VOHL: a VLSI object-oriented hardware language

“…The flexibility provided in VHDL for providing the different levels of abstraction also hinders it for logic synthesis applications. The flexible timing models in VHDL breed confusion for a user (see [6]). All these reasons have contributed to a very slow acceptance of VHDL.…”