A procedure for software synthesis from VHDL models

Abstract

In this paper we address the problem of software generation from a Hardware Description Language (HDL). In particular, we examine the issues involved in translating VHDL into C or C++ for use in system simulation and cosynthesis. Because of the concurrency supported by VHDL, and a notion of timing behavior, care must be taken to ensure behavioral correctness of the generated software. The issues involved will be shown to be different in each of the application areas. The ideas set forth here have been used in an efficient VHDL simulator designed to execute on multiprocessor systems. Results are presented for simulation on uniprocessor as well as multiprocessor systems.

Retargetable compiled simulation of embedded processors using a machine description language

“…However, the reported simulation speed of 500-800 instructions on a Sparc 2 workstation is rather low for application software design. An approach of translating event-driven VHDL models into C++ simulators has been reported [Krishnaswamy et al 1999], but the achieved simulation speed-up is comparatively low and the absolute speed is far from our requirements.…”