Timing Analysis of Computer Hardware

Abstract

Timing Analysis of Computer Hardware Timing Analysis is a design automation program that assists computer design engineers in locating problem timing in a clocked, sequential machine. The program is effective for large machines because, in part, the running time is proportional to the number of circuits. This is in contrast to alternative techniques such as delay simulation, which requires large numbers of test patterns, and path tracing, which requires tracing of all paths. The output of Timing Analysis includes 'Slack" at each block to provide a measure of the severity of any timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach. This system has successfully detected all but a few timing problems for the IBM 3081 Processor Unit (consisting of almost 800 000 circuits) prior to the hardware debugging of timing. The 3081 is characterized by a tight statistical timing design. abstract may be used without further permission in computer-based and other information-service systems. Permission to republish other excerpts should be obtained from the Editor.

Gate sizing for large cell-based designs

“…The timing constraints we consider are based on static timing analysis [9] with slew propagation. The signal propagation is described by a directed timing graph G T on the set of pins (V (G T ) = P ).…”

Timing Driven Placement for Large Standard Cell Circuits

“…The total timing penalty is just the sum over all critical paths: (10) The simulated annealing cost function C consists of two terms. The first term is the total wire length, represented by W. The second term is the timing path penalty function .…”

“…The user may remove any false paths by enumerating them in a file. This is similar to the TA timing analyzer which allowed the user to add delay modifiers to indicate that a path was not possible [10]. The false paths may be obtained by using external timing analyzers.…”

Equivalent waveform propagation for static timing analysis

“…STA is a procedure used to calculate the LAT of signal transitions at each node in a circuit and propagate it to the next gate [5]. Input waveform shape is an important factor that affects gate delay.…”

“…Throughout this paper, we assume that the distorted input waveform applied to the gate can be obtained by other methods, such as [1], and focus on the problem of finding the equivalent waveform from which we can derive the LAT and the slope for gate delay calculation. Once the LAT and slope are obtained, the path delay can be calculated, for example, by [4] and [5].…”