Timing analysis of combinational circuits using ADDs

Bahar, R. Iris; Cho, H.; Hachtel, Gary D.; Macii, Enrico; Somenzi, Fabio

doi:10.1109/edtc.1994.326813

Cited by 24 publications

(10 citation statements)

References 15 publications

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“…We express weights as binary weight values d= d m-1 ,…d 0 and the matrix can be represented by a collection of matrices taken for each weight bit. Since the Boolean expressions are for weight values, the computations are easier and faster compared to ADDs [3]. The matrix of the weight bit d0 is nothing but BDD representation.…”

Section: Reduction Rulesmentioning

confidence: 99%

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Timing analysis of combinational circuits using Weights Binary Decision Diagram (WBDD)

Bhuvaneswari

Prasad

Singh

et al. 2010

2010 International Conference on Electronic Devices, Systems and Applications

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Weights Binary Decision Diagram (WBDD) based timing analysis of combinational circuit is proposed. Here we express the combinational circuit as a directed graph. We compute and store the delay of combinational circuits for all combination of inputs for the range of delay values based on controlling values. Hence it is possible to look up the built in library and calculate the output delay of any combinational circuit. The output delay computation is much faster when compared to normal method of calculating the delay at each level of the combinational circuits. This can be used in the synthesis of network for low power consumption.

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Section: Reduction Rulesmentioning

confidence: 99%

“…In [3] a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of Algebraic Decision Diagram (ADD's) is given. This approach does not require any explicit false path elimination.…”

Section: Introductionmentioning

confidence: 99%

Timing analysis of combinational circuits using Weights Binary Decision Diagram (WBDD)

Bhuvaneswari

Prasad

Singh

et al. 2010

2010 International Conference on Electronic Devices, Systems and Applications

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“…The first problem of standard approaches of [6,11,13,14] relates to considering only the combinational portion of the circuit. These methods ignore sequential behavior and often overestimate the delay value.…”

Section: Introductionmentioning

confidence: 99%

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

Mondal

Chakrabarti

Dasgupta

2007

2007 International Conference on Computing: Theory and Applications (ICCTA'07)

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Accurate timing information of circuits is essential for high quality designs. This paper presents a symbolic event propagation based method to determine the critical delay of digital circuits. The proposed approach considers the effect of glitches, multiple transitions and simultaneous switching on the critical delay. Our method identifies and eliminates both combinational and sequential false paths. We also consider triggering of traditional combinational false paths due to multiple transitions. The mathematical formulation makes no assumption about the start state of the finite state machine extracted from the sequential circuit. Few approximate methods have been proposed to determine the upper bound of the critical delay. A complete BDD based implementation has been made. Results on ISCAS89 benchmark circuits are presented.

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“…Then, the problem of timed ATPG can be solved by running an SAT solver [12][13] [15] [18] or an ATPG engine on the corresponding TCF. [2] proposed to use ADD, a data structure similar to BDD, to represent the relation between each input vector and its corresponding output arrival time. The results show that the method is not usable for large circuits due to the high computation cost.…”

Section: Introductionmentioning

confidence: 99%

Efficient Boolean Characteristic Function for Fast Timed ATPG

Kuo¹,

Chang²,

Chang³

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Circuit timing analysis is important in various aspects of circuit optimization. The problem of finding input vectors achieving functional and temporal requirements is known as timed Automatic Test Pattern Generation (timed ATPG). A timed ATPG algorithm will return an input vector that satisfies functional and temporal requirements simultaneously when evaluated. Several previous works use timed ATPG as a core engine for solving problems related to timing analysis, such as crosstalk and maximum instantaneous current analysis. Despite the usefulness of timed ATPG, traditional timed ATPG is slow and unscalable for large circuits. In this paper, we present a very efficient way for timed ATPG. On average, our results are 8 times faster than the most recent work, and in some cases, up to 32 times faster.

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Timing analysis of combinational circuits using ADDs

Cited by 24 publications

References 15 publications

Timing analysis of combinational circuits using Weights Binary Decision Diagram (WBDD)

Timing analysis of combinational circuits using Weights Binary Decision Diagram (WBDD)

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

Efficient Boolean Characteristic Function for Fast Timed ATPG

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