Time to Digital Sensing for Multilevel RRAM Cells

Abstract

Memristors offer the possibility of implementing multilevel cells in Resistive RAMs providing high-density non-volatile data storage solutions. However the writing and reading processes when these devices are integrated into a crossbar is a problem that has not yet been fully solved. Process and temperature variations must be carefully handled when designing reliable interface circuits for RRAM cells. In this work we present a time-domain reading circuit for multilevel RRAM cells. The sensing operation is performed based on the well-known RC circuit that generates a pulse whose width depends on the state of the cell, providing excellent results in terms of area, energy per bit and scalability. Temperature and process variations have been analysed in depth to validate the effective number of levels a cell may store to be read accurately.

Comparison of 1T1R and 1C1R ReRAM Arrays

“…The design of readout circuits has been the subject of extensive studies due to the challenges of current solutions [9][10][11]. In this comparison, we compare the complexity of the most common readout solution for 1T1R, and readout technique used in 1C1R.…”

“…In this comparison, we compare the complexity of the most common readout solution for 1T1R, and readout technique used in 1C1R. for readout [9]. The TIA is used to sense the current passing through the device under test (DUT) and convert to voltage, then an ADC is followed to digitize the sensed voltage [12].…”