Time to digital converter based on a 2-dimensions Vernier architecture

Liscidini, Antonio; Vercesi, Luca; Castello, R.

doi:10.1109/cicc.2009.5280922

Cited by 52 publications

(16 citation statements)

References 3 publications

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“…LSK -Vernier vėlinimo linijoje yra naudojamos dvi vėlinimo linijos, sudarytos iš vėlinimo elementų, turinčių skirtingas vėlinimo trukmes (7 pav.) (Liscidini et al 2009). Per vieną liniją yra siunčia-mas DS generuojamas signalas, per kitą -atraminis signalas.…”

Section: Lsk Struktūros Tobulinimasunclassified

Increasing a Resolution of Time to Digital Converter

Jurgo

Navickas

2017

Science - Future of Lithuania

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2017 © Straipsnio autoriai. Leidėjas VGTU leidykla "Technika". Šis straipsnis yra atvirosios prieigos straipsnis, turintis Kūrybinių bendrijų (Creative Commons) licenciją (CC BY-NC 4.0), kuri leidžia neribotą straipsnio ar jo dalių panaudą su privaloma sąlyga nurodyti autorių ir pirminį šaltinį. Straipsnis ar jo dalys negali būti naudojami komerciniams tikslams. Reikšminiai žodžiai: laikinis skaitmeninis keitiklis, skiriamoji geba, vėlinimo trukmė, KMOP. MOKSLAS -LIETUVOS ATEITIS SCIENCE -FUTURE OF LITHUANIA ĮvadasLaikinis skaitmeninis keitiklis -tai įtaisas, suteikiantis laiko tarpui tarp dviejų signalų frontų skaitmeninę išraiš-ką (Staszewski et al. 2006). Pastaruoju metu jis dažnai naudojamas kaip fazės detektorius visiškai skaitmeninėse fazės derinimo kilpose (FDK), atliekančiose dažnio sintezatoriaus (DS) funkciją įrengtuose dažnio sintezatoriuose (DS) (1 pav.). Pats paprasčiausias LSK yra paremtas inverterių vėli-nimo linija (2 pav.) (Staszewski et al. 2006;Effendrik et al. 2011). Jame SVG generuojamas signalas sklinda inverterių vėlinimo linija, o atraminio signalo frontu šis signalas 1 pav. Supaprastinta visiškai skaitmeninio dažnio sintezatoriaus struktūra: SVG -skaitmeniniu būdu valdomas generatorius, LSK -laikinis skaitmeninis keitiklis fiksuojamas po kiekvieno vėlinimo elemento. LSK išėjime yra gaunamas pseudotermometrinis kodas, kurį iškodavus gaunama informacija apie laiko tarpą, skiriantį atraminio ir generuojamo signalo frontus. Mažiausias laiko tarpas, kurį galima pamatuoti tokiu LSK, yra inverterio vėlinimo trukmė t res = Δt inv , o LSK skiriamoji geba:LSK išėjimo signalas yra skaitmeninis, todėl jis dažnio sintezatoriaus išėjime sukuria kvantavimo triukš-mą. Yra išvesta analitinė LSK kuriamo mažiausio fazės triukšmo lygio DS artimojoje srityje (angl. in-band) išraiška

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Section: Lsk Struktūros Tobulinimasunclassified

Increasing a Resolution of Time to Digital Converter

Jurgo

Navickas

2017

Science - Future of Lithuania

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“…According to (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15), the input signals of stages 2-4 are calculated as:…”

Section: E®ect Of a Mismatch Error On The Performance Of The Convertermentioning

confidence: 99%

“…In order to improve time resolution, Vernier delay-line (VDL) TDC can be adopted which has sub-gate delay resolution. 6,7 These converters are used to measure short time intervals between the rising edges of the input signals. VDL and delay-line TDCs are sensitive to PVT variations.…”

Section: Introductionmentioning

confidence: 99%

A New Triple-Slope Pipelined Time to Digital Converter by Stretching of Time

Rezvanyvardom

Farshidi

2015

J CIRCUIT SYST COMP

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This study investigates a novel approach for pipeline time-to-digital converters (TDCs) which employs analog interpolation and time stretching techniques for digitizing the time interval between two input signals as well as increasing resolution. In the proposed converter, analog interpolation is performed based on a triple-slope conversion. This converter will be a 9-bit pipeline TDC which contains three time stretching ampli¯ers (TSAs) and four 2.5-b/stage TDCs. This converter does not use delay lines in its structure. It features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations and high accuracy compared with the TDCs which have previously been proposed. Also, the time resolution, the dynamic range and the linear range of the TDC are improved. The proposed structure reduces the active chip area, the power consumption and the¯gure of merit (FoM). In addition, the integral nonlinearity (INL) and the di®erential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the TDC is designed in TSMC 45-nm CMOS technology and simulated. Comparison of the theoretical and simulation results con¯rms the bene¯ts of the proposed TDC.

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“…Direct conversion TDCs employ delay-line elements which include a chain of buffers or inverters in their structure. These converters are used to measure short time intervals between the rising edges of the input signals [7], [8]. The main disadvantages of direct conversion TDCs are the circuit complexity, which results in high power consumption and high sensitivity to PVT variations [9].…”

Section: Introductionmentioning

confidence: 99%

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

Farshidi¹,

Rezvanyvardom²

2015

RADIOENGINEERING

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This paper investigates a novel cyclic time-todigital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals (Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT) variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. This converter also improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the integral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

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Time to digital converter based on a 2-dimensions Vernier architecture

Cited by 52 publications

References 3 publications

Increasing a Resolution of Time to Digital Converter

Increasing a Resolution of Time to Digital Converter

A New Triple-Slope Pipelined Time to Digital Converter by Stretching of Time

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

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