Time redundant error correcting adders and multipliers

Hsu, Yuang-Ming; Swartzlander, Earl E.

doi:10.1109/dftvs.1992.224350

Cited by 31 publications

(8 citation statements)

References 4 publications

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“…After the publication of the REDWC method, three independent extensions from error detection to error correction were presented [7,8,9]. The method described in [7] is called Hardware Partition in Time Redundancy (HPTR).…”

Section: : Concurrent Error Correctionmentioning

confidence: 99%

“…Not only are the adder modules affected by this "padding," but also wider 3:1 multi plexers and voters are needed, further increasing the hardware overhead. In addition, while HPTR requires two control signals with one unused combination [7], another method uses a one-hot encoding of three control signals [8].…”

Section: : Quadruple Time Redundancymentioning

confidence: 99%

“…The method described in [7] is called Hardware Partition in Time Redundancy (HPTR). In [8] the method is called REcomputing with Tr iplication With Voting (RETWV) and in later work [10] this method is called Time Shared Triple Modular Redundancy (TSTMR). In [9], the method is called Recomputing With Partitioning and Voting (RWPV).…”

Section: : Concurrent Error Correctionmentioning

confidence: 99%

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Quadruple time redundancy adders [error correcting adder]

Townsend

Abraham

Swartzlander³

Proceedings. 16th IEEE Symposium on Computer Arithmetic

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This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Triple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% -55% reduction in hardware complexity while incurring a reasonable delay zncrease.

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Section: : Concurrent Error Correctionmentioning

confidence: 99%

Section: : Quadruple Time Redundancymentioning

confidence: 99%

Section: : Concurrent Error Correctionmentioning

confidence: 99%

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Quadruple time redundancy adders [error correcting adder]

Townsend

Abraham

Swartzlander³

Proceedings. 16th IEEE Symposium on Computer Arithmetic

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“…uniprocessor) and the main focus is on the effect of fault tolerance on the response time of the system. Examples of timeredundant approaches for application to arithmetic computation can be found in [4].…”

Section: International Workhop On Defect and Fault Tolerance In Vlsimentioning

confidence: 99%

“…For fault tolerant computing purposes, by carefully scheduling the recomputation of the secondary version of a job, fault detection can be obtained using time redundancy at no significant increase in processing time. In this paper, the t e n "job is used in a general context to identify a computation process which may consists of a single step as in [4] or a series of steps as in [3].…”

Section: Review and Preliminariesmentioning

confidence: 99%

Scheduling policies for fault tolerance in a VLSI processor

Shen

Kari²,

Kim³

et al.

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions of each job must be processed. A discrepancy in the results produced by comparing the outcomes of the two versions of the same job indicates that a fault may have occurred. Several methods for appropriately scheduling the primary and secondary versions of the jobs are proposed and analyzed. Introduction.To meet the increasing demand of system reliability and availability, fault tolerant techniques have been widely employed in today's computers [l]. One of the arrangements commonly employed for achieving fault tolerance consists of providing some form of redundancy in the system. Redundancy can be applied in either the hardware (for example by using a duplex or a higher module replication) or in the software (as the N version programming redundancy of [2]). This type of redundancy is referred to as space redundancy. As in a redundant system, replication of at least twice the hardware or software components is required, then the cost of manufacturing fault tolerant computing systems in VLSI can be expected to increase substantially [l]. Another interesting method for attaining fault tolerant computing is time redundancy [I]; an example of this type of approach is the recomputation with shifted operands (RESO) [3], in which fault tolerance is achieved by limiting the modular replication of space redundancy, but at least doubling the time required for the basic computation step.In a multi-processor system, processors provide some natural form of space redundancy. Studies have shown thet demand for system resources varies in a stochastic manner, in most cases a so-called spare capacity exists to implement some form of space redundancy [5].

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