Time-dependent dielectric breakdown of gate oxide on 4H-SiC with different oxidation processes

Tsui, Bing-Yue; Huang, Yi; Wu, Tian-Li; Chien, Chia-Hung

doi:10.1016/j.microrel.2021.114186

Cited by 10 publications

(5 citation statements)

References 43 publications

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“…The interface trap densities D it for the samples after post-oxidation processes are presented in Figure 1 c. These are compared for the energy of 0.2 eV below the conduction band and included in Table 2 . The trap density D it behavior of the NO-annealed sample is consistent with previous data [ 20 , 24 , 49 ]. However, the results for the POCl 3 -annealed sample must be discussed.…”

Section: Resultssupporting

confidence: 91%

“…Nitridation of SiO 2 /SiC interfaces at lower temperatures was extensively studied in an oxynitride or a nitric oxide environment [ 20 , 21 , 22 ], but different impacts on the density of interface trap states were noted [ 23 ]. The nitridation process not only reduces the D it but can also improve the gate oxide reliability [ 24 ]. Experimental works have shown that high-temperature processes at the SiO 2 /SiC interface are complicated, and the results are not easily repeatable on different SiO 2 /SiC structures.…”

Section: Introductionmentioning

confidence: 99%

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Carrier Trap Density Reduction at SiO2/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres

et al. 2023

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The electrical and physical properties of the SiC/SiO2 interfaces are critical for the reliability and performance of SiC-based MOSFETs. Optimizing the oxidation and post-oxidation processes is the most promising method of improving oxide quality, channel mobility, and thus the series resistance of the MOSFET. In this work, we analyze the effects of the POCl3 annealing and NO annealing processes on the electrical properties of metal–oxide–semiconductor (MOS) devices formed on 4H-SiC (0001). It is shown that combined annealing processes can result in both low interface trap density (Dit), which is crucial for oxide application in SiC power electronics, and high dielectric breakdown voltage comparable with those obtained via thermal oxidation in pure O2. Comparative results of non-annealed, NO-annealed, and POCl3-annealed oxide–semiconductor structures are shown. POCl3 annealing reduces the interface state density more effectively than the well-established NO annealing processes. The result of 2 × 1011 cm−2 for the interface trap density was attained for a sequence of the two-step annealing process in POCl3 and next in NO atmospheres. The obtained values Dit are comparable to the best results for the SiO2/4H-SiC structures recognized in the literature, while the dielectric critical field was measured at a level ≥9 MVcm−1 with low leakage currents at high fields. Dielectrics, which were developed in this study, have been used to fabricate the 4H-SiC MOSFET transistors successfully.

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Section: Resultssupporting

confidence: 91%

Section: Introductionmentioning

confidence: 99%

Carrier Trap Density Reduction at SiO2/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres

et al. 2023

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“…Apparent electron trap is observed on all samples and then the gate oxide breakdown. This is the typical phenomenon of the NO annealed gate oxide on SiC [5]. Fig.…”

Section: Resultsmentioning

confidence: 69%

Influence of Post-Ion-Implantation Annealing Temperature on the Characteristics of Gate Oxide on 4H Silicon Carbide

Lin

Tsui

2023

MSF

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The effect of post-ion implantation annealing on the properties of the SiO2/4H-SiC interface is examined in this paper. It is observed that the surface roughness degrades after the high-temperature Ar annealing, but the oxidation process after the high temperature annealing can improve the surface roughness. To better understand the effect of high-temperature annealing on the gate oxide, the reliability of gate oxide is further studied. The results show that although the surface roughness degrades after high-temperature annealing, the interface state density, tunneling barrier height, breakdown field, and critical electric field for the 10-year lifetime of the thermally grown gate oxide do not degrade.

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“…The ∆Vth as well as ∆ID are minor for devices with pure NO annealing process. Adequate amount of NO annealing was suggested to be effective in passivating carbon interstitials which act as hole traps [10,17]. Still, under -10 V stress condition (NBS) both POA conditions exhibit significant negative ∆Vth and the ∆ID increases for NMOSFET while decreases for PMOSFET.…”

Section: Resultsmentioning

confidence: 99%

Bias-Induced Instability of 4H-SiC CMOS

Wen

Tsui

2023

MSF

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4H-SiC complementary metal-oxide-semiconductor (CMOS) devices for control circuit applications have been reported extensively, however, the electrical stability, even with interface optimization processes, degrades significantly after bias stress. In this paper, we performed both positive and negative bias stress on planar SiC NMOSFETs and PMOSFETs fabricated with pure (non-diluted) and N2-diluted NO post-oxidation annealing (POA) processes. The test results indicate the existence of positive hole traps might be the culprit that leads to electrical characteristics instability during operation and pure NO annealing is effective to reduce the instability.

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Time-dependent dielectric breakdown of gate oxide on 4H-SiC with different oxidation processes

Cited by 10 publications

References 43 publications

Carrier Trap Density Reduction at SiO2/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres

Carrier Trap Density Reduction at SiO2/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres

Influence of Post-Ion-Implantation Annealing Temperature on the Characteristics of Gate Oxide on 4H Silicon Carbide

Bias-Induced Instability of 4H-SiC CMOS

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