Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements

Lelis, Aivars J.; Habersat, Daniel B.; Green, R.; Ogunniyi, Aderinto; Gurfinkel, M.; Suehle, John S.; Goldsman, N.

doi:10.1109/ted.2008.926672

Cited by 279 publications

(169 citation statements)

References 30 publications

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“…The observations that we have made here are largely consistent with similar experiments on Si, SiC and III-V MOSFETs [15][16][17][18]. ∆VT appears to take place due to two mechanisms.…”

Section: B Modelsupporting

confidence: 91%

“…13). For the SiO2 system, β = 0.25 and τ0 = 150 s provides a reasonable match at all T. The β values extracted here are close to those reported in the literature: β = 0.2 ~ 0.32 [15][16][17][18].…”

Section: B Modelsupporting

confidence: 86%

“…9 shows long recovery time constant). Stress time evolution of VT follows a saturating log-time dependence, as observed in other MOS systems [15][16][17]19]. The slight decrease in IG also indicates that no additional traps are generated in the oxide bulk [19].…”

Section: A Mechanisms Responsible For Vt Shift Under Pbtisupporting

confidence: 66%

“…This phenomenon has been intensively studied in Si, SiC and various III-V MOS systems where it is sometimes referred to as bias-temperature instability (BTI) [12][13][14][15][16][17][18]. In Si n-channel MOSFETs with high-k gate dielectric, Positive Bias Temperature Instability (PBTI) is known to be caused by electron trapping in pre-existing oxide traps that causes a positive VT shift [12,13].…”

Section: Introductionmentioning

confidence: 99%

“…Negative-bias temperature instability (NBTI) in p-channel MOSFETs is related to interface state generation and hole trapping in the gate dielectric [14]. In SiC MOSFETs, periodic VT shifts under alternating positive and negative gate stress have been observed and attributed to electron tunneling in and out of near-interface oxide traps [15]. InGaAs n-MOSFETs with a high-k dielectric also have shown positive VT shifts after positive gate stress.…”

Section: Introductionmentioning

confidence: 99%

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Positive-bias temperature instability (PBTI) of GaN MOSFETs

Alamo

2015

2015 IEEE International Reliability Physics Symposium

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-We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO2 or a composite SiO2/Al2O3 bilayer were studied. Our research has targeted the evolution of threshold voltage (VT), subthreshold swing (S) and transconductance (gm) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive VT shift (∆VT) in both gate dielectrics under positive gate stress. In devices with a SiO2 gate oxide, we have found that ∆VT is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO2/Al2O3 gate oxide, on the other hand, ∆VT is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.

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“…The observations that we have made here are largely consistent with similar experiments on Si, SiC and III-V MOSFETs [15][16][17][18]. ∆VT appears to take place due to two mechanisms.…”

Section: B Modelsupporting

confidence: 91%

Section: B Modelsupporting

confidence: 86%

Section: A Mechanisms Responsible For Vt Shift Under Pbtisupporting

confidence: 66%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Positive-bias temperature instability (PBTI) of GaN MOSFETs

Alamo

2015

2015 IEEE International Reliability Physics Symposium

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Device Processing of Silicon Carbide

Kimoto¹,

Cooper

2014

Fundamentals of Silicon Carbide Technology

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Influence Mechanism of Barium Interface Layer on the Interfacial Properties of n‐Type 4H‐SiC Metal–Oxide–Semiconductor Capacitors

Bai

Tang

Zhang

et al. 2020

Physica Status Solidi (b)

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The 4H‐SiC/SiO2 interface quality can be significantly improved by adding an alkaline earth metal interface layer. To study the passivation mechanism of the alkaline earth metal barium (Ba), a supercell model with a transition layer is established. As shown in the results from first‐principles calculations, the bandgap increases and the density of states decreases when SiBaO or OBaO structures are introduced into the transition layer. 4H‐SiC/Ba interface layer/SiO2 capacitors with different annealing conditions are fabricated. X‐ray photoelectron spectroscopy results show that Ba mainly exists in the form of BaO2 (corresponding to the OBaO structure) after annealing in 5% O2 in Ar atmosphere, and there are fewer types of suboxides in the interface than those annealed in Ar. A small amount of Ba also combines with SiO2 to form SiBaxOy compounds (corresponding to the SiBaO structure). The correctness of the theoretical analysis is verified by capacitance–voltage measurements. The physical mechanism of Ba passivation is analyzed in this article, which helps to improve the performance of SiC metal–oxide–semiconductor (MOS) structure devices.

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Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements

Cited by 279 publications

References 30 publications

Positive-bias temperature instability (PBTI) of GaN MOSFETs

Positive-bias temperature instability (PBTI) of GaN MOSFETs

Device Processing of Silicon Carbide

Influence Mechanism of Barium Interface Layer on the Interfacial Properties of n‐Type 4H‐SiC Metal–Oxide–Semiconductor Capacitors

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