Time-constrained code compaction for DSPs

Leupers, Rainer; Marwedel, Peter

doi:10.1109/isss.1995.520613

Cited by 14 publications

(4 citation statements)

References 12 publications

(4 reference statements)

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“…In contrast to previous research [1], [12], [2], [8], [9] which examined the general offset assignment problem or other addressing techniques, we have presented an optimal polynomial time technique for generating address code which can work in conjunction with any data memory layout technique such as in [2] or with memory layout generated by a compiler. This may be advantageous when memory layout is constrained by interfacing with external systems or when it is performed by an algorithm the user has selected and does not wish to change.…”

Section: Discussionmentioning

confidence: 99%

A minimum-cost circulation approach to DSP address-code generation

Gebotys

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents a new approach to solving the DSP address code generation problem. A minimum cost circulation approach is used to efficiently generate high-performance addressing code in polynomial time. Results show that addressing code size improvements of up to 62 are obtained, accounting for up to 1:62 improvement in code size and performance of compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size, energy dissipation, and performance, without increasing cost. Index Terms-Digital signal processors, optimization methods, optimizing compilers, program compilers. I. INTRODUCTION A S digital signal processing (DSP) applications are rapidly growing more complex, some designers are moving from full custom digital circuitry to programmable processors or in-house cores to obtain lower risk solutions. The DSP core is a DSP processor that can be reused and combined with program/data memory, dedicated logic, plus applicationspecific integrated circuits (ASIC's), and incorporated onto a large silicon chip, providing a cost efficient and flexible solution for many typical embedded applications requiring low power and high reliability. These systems demand small code size and high-performance. Due to increasing complexities, high-level compilation is a necessity. However, the biggest drawback to both DSP processors or DSP core use is the code generation. The use of conventional code generation techniques and even compilers specifically designed for commercial DSP processors produce very inefficient code [2], [4], [24]. There are many more limitations placed upon code generation for the DSP processor than for the general-purpose processor. The difficulty arises from nonhomogeneous register sets, small number of very specialized registers, very specialized functional units, restricted connectivity, limited addressing, and highly irregular datapaths [1]. For example specialized functional units such as address calculation units are typically found in these architectures. Instructions take operands and store results of computations in well defined registers with limited connectivity.

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Section: Discussionmentioning

confidence: 99%

A minimum-cost circulation approach to DSP address-code generation

Gebotys

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Inspired by early work on IP-based scheduling for high-level synthesis [64,85], Leupers and Marwedel introduce an IP model that includes alternative instruction versions and side effect handling for irregular, multiple-issue DSPs [111]. Alternative instruction versions (called alternative encodings by Leupers and Marwedel) supports the selection of different instruction implementations, each using different resources, for each input instruction.…”

Section: Local Instruction Schedulingmentioning

confidence: 99%

Survey on Combinatorial Register Allocation and Instruction Scheduling

Lozano

Schulte

2019

ACM Comput. Surv.

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Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the past three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This article provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization.

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“…If all outgoing edges from a node i are covered by a pattern instance p, there is no need to store the value represented by i in a register. Equation (10) requires solution variable r i,t to be set to 0 if all outgoing edges from i are inactive at time t.…”

Section: Register Allocationmentioning

confidence: 99%

“…Gebotys et al [5] give a time-based formulation that integrates instruction scheduling and resource allocation and computes time optimal schedules. Leupers and Marwedel [10] provide a time-based ILP formulation for code compaction of a given instruction sequence with alternative instruction encodings.…”

Section: Introductionmentioning

confidence: 99%

Optimal Integrated VLIW Code Generation with Integer Linear Programming

Bednarski

Keßler

2006

Euro-Par 2006 Parallel Processing

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We give an Integer Linear Programming (ILP) solution that fully integrates all steps of code generation, i.e. instruction selection, register allocation and instruction scheduling, on the basic block level for VLIW processors.In earlier work, we contributed a dynamic programming (DP) based method for optimal integrated code generation, implemented in our retargetable code generator OPTIMIST. In this paper we give first results to evaluate and compare our ILP formulation with our DP method on a VLIW processor. We also demonstrate how to precondition the ILP model by a heuristic relaxation of the DP method to improve ILP optimization time.

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Time-constrained code compaction for DSPs

Cited by 14 publications

References 12 publications

A minimum-cost circulation approach to DSP address-code generation

A minimum-cost circulation approach to DSP address-code generation

Survey on Combinatorial Register Allocation and Instruction Scheduling

Optimal Integrated VLIW Code Generation with Integer Linear Programming

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