A minimum-cost circulation approach to DSP address-code generation

Abstract

This paper presents a new approach to solving the DSP address code generation problem. A minimum cost circulation approach is used to efficiently generate high-performance addressing code in polynomial time. Results show that addressing code size improvements of up to 62 are obtained, accounting for up to 1:62 improvement in code size and performance of compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size, energy dissipation, and performance, without increasing cost. Index Terms-Digital signal processors, optimization methods, optimizing compilers, program compilers. I. INTRODUCTION A S digital signal processing (DSP) applications are rapidly growing more complex, some designers are moving from full custom digital circuitry to programmable processors or in-house cores to obtain lower risk solutions. The DSP core is a DSP processor that can be reused and combined with program/data memory, dedicated logic, plus applicationspecific integrated circuits (ASIC's), and incorporated onto a large silicon chip, providing a cost efficient and flexible solution for many typical embedded applications requiring low power and high reliability. These systems demand small code size and high-performance. Due to increasing complexities, high-level compilation is a necessity. However, the biggest drawback to both DSP processors or DSP core use is the code generation. The use of conventional code generation techniques and even compilers specifically designed for commercial DSP processors produce very inefficient code [2], [4], [24]. There are many more limitations placed upon code generation for the DSP processor than for the general-purpose processor. The difficulty arises from nonhomogeneous register sets, small number of very specialized registers, very specialized functional units, restricted connectivity, limited addressing, and highly irregular datapaths [1]. For example specialized functional units such as address calculation units are typically found in these architectures. Instructions take operands and store results of computations in well defined registers with limited connectivity.

A network flow approach to memory bandwidth utilization in embedded DSP core processors

“…A number of researchers have examined allocation of address registers [5], [6], data layout [1], and index registers [7]. Researchers in [2] introduced a transformation of C code, using pointer based code instead of array based code to make better use of address calculation units on DSPs.…”

“…Register allocation, binding, and scheduling techniques are discussed in [9]. A network flow formulation in [6] was used to allocate address registers for DSP processors with significant savings in code size. Researchers in [10] perform register binding and instruction scheduling to minimize the number of registers and find tight schedules through the addition of sequencing relations.…”

Optimal general offset assignment

“…This was shown by Gebotys [9,10] who provided a minimum-cost circulation algorithm that we will discuss in more detail in Sect. 3.1.…”

A framework for computation-memory algorithmic optimization for signal processing

“…[1], [2] are examples of retargetable compilers that can generate efficient code given a description of the machine architecture. [3] proposes a graph-based optimization technique to generate digital signal processor (DSP) address code. [4] mixes models of computation-imperative programming language such as C and signal processing specific model such as synchronous data flow (SDF), for optimal DSP compilation while offering intuitive user appeal.…”