A network flow approach to memory bandwidth utilization in embedded DSP core processors

Gebotys, Catherine H.

doi:10.1109/tvlsi.2002.807766

Cited by 4 publications

(4 citation statements)

References 14 publications

(14 reference statements)

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“…The SPA-resistant ECC was implemented in both binary and prime fields. The algorithm was coded using both "C" and assembly (to take full advantage of the high memory bandwidth [Gebotys 2002] and complex functional units of Star*Core DSP processor core) using the methodology described in Section 3. In this section, small keys will be used to illustrate the design for security methodology, however, the developed ECC codes perform well in practical applications and have been fully verified.…”

Section: Methodsmentioning

confidence: 99%

“…All power traces were obtained by executing the cryptographic algorithms on the SC140 at 100 MHz (for illustration purposes, although 300 MHz power traces showed almost identical power variation), using a pattern generator and high speed oscilloscope to capture the power traces as described in Muresan et al [2001] and Muresan et al [2002]. The SC140 has four multiplier-accumulator units, high memory bandwidth [Gebotys 2002], and a VLIW architecture [Motorola/Lucent 1999] with a supply voltage of 2 V. It has a 16 bit instruction, 40 bit data registers, and a 128 bit data bus, where four 32 bit words can be loaded or stored from/to memory in one cycle. Matlab was used for signal analysis of the power waveforms and GAMS for solving the ILP.…”

Section: Methodsmentioning

confidence: 99%

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Design of secure cryptography against the threat of power-attacks in DSP-embedded processors

Gebotys

2004

ACM Trans. Embed. Comput. Syst.

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Embedded wireless devices require secure high-performance cryptography in addition to low-cost and low-energy dissipation. This paper presents for the first time a design methodology for security on a VLIW complex DSP-embedded processor core. Elliptic curve cryptography is used to demonstrate the design for security methodology. Results are verified with real dynamic power measurements and show that compared to previous research a 79% improvement in performance is achieved. Modification of power traces are performed to resist simple power analysis attack with up to 39% overhead in performance, up to 49% overheads in energy dissipation, and up to 11% overhead in code size. Simple power analysis on the VLIW DSP core is shown to be more correlated to routine ordering than individual instructions. For the first time, differential power analysis results on a VLIW using real power measurements are presented. Results show that the processor instruction level parallelism and large bus size contribute in making differential power analysis attacks extremely difficult. This research is important for industry since efficient yet secure cryptography is crucial for wireless communication devices.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Design of secure cryptography against the threat of power-attacks in DSP-embedded processors

Gebotys

2004

ACM Trans. Embed. Comput. Syst.

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“…To improve system performance and data efficiency, C.H. Gebotys' 2002 introduces a network flow-based strategy to optimize memory bandwidth utilization in embedded DSP core processors [10]. Donghoon et al [11] designed a robust 16-bit DSP with advanced features, including a 40-bit ALU, a six-level pipeline, and a 17 × 17 parallel multiplier.…”

Section: Existing Workmentioning

confidence: 99%

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Mohanarangam,

M Shirur

et al. 2023

Electronics

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Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

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“…Based on the instruction types and the usage of the upper bank registers within an execution set the instructions are serially grouped or prefix grouped by the assembler [1]. Unlike other DSP processor cores, the SC140 can load or store eight sixteen bit words per cycle (providing a high data memory bandwidth [2]). In this paper we introduce a methodology for developing an empirical instructionbased model which is capable of estimating dynamic current, power or energy consumption for a DSP processor core.…”

Section: Introductionmentioning

confidence: 99%

Modeling Power Dynamics for an Embedded DSP Processor Core

Gebotys

Mureşan

2002

IFIP Advances in Information and Communication Technology

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A new model for dynamic current analysis and simulation is presented for power and energy analysis of a complex VLIW DSP processor core, targeting secure wireless communications. Unlike other research, an instruction level RC based model, whose input parameters can be extracted from the DSP core's assembly level program, is introduced for power simulation. Experimental results utilizing several benchmark cryptographic applications show that the model can accurately simulate power variation of a program. For the first time results are verified with real power traces of a DSP processor core in a VLSI chip running cryptographic applications with an average error in energy estimation of 7%. This research is important for analyzing the impact of software on power and the design of embedded cryptographic VLSI systems that are safe from power attacks.

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A network flow approach to memory bandwidth utilization in embedded DSP core processors

Cited by 4 publications

References 14 publications

Design of secure cryptography against the threat of power-attacks in DSP-embedded processors

Design of secure cryptography against the threat of power-attacks in DSP-embedded processors

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Modeling Power Dynamics for an Embedded DSP Processor Core

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