Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories

Trinh, Quang-Kien; Ruocco, Sergio; Alioto, Massimo

doi:10.1109/tcsi.2018.2828611

Cited by 28 publications

(24 citation statements)

References 20 publications

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“…Therefore, it is ideal for the proposed majority gate. Furthermore, this time-based sensing achieves two to three orders of magnitude improvement in sensing (BER) compared to conventional schemes, in addition to being reference-less [17].…”

Section: B Sensing Methodologymentioning

confidence: 98%

“…It must be noted that this will be exacerbated by the variability exhibited by the RRAM devices. To meet this requirement, a time-based SA recently proposed in [17] was chosen. Different from conventional sensing schemes (voltagemode and current-mode), the time-based sensing scheme converts the BL voltage (to be sensed) into a time delay and discriminates in time-domain.…”

Section: B Sensing Methodologymentioning

confidence: 99%

“…Different from conventional sensing schemes (voltagemode and current-mode), the time-based sensing scheme converts the BL voltage (to be sensed) into a time delay and discriminates in time-domain. This sensing scheme was originally proposed to read data from STT-MRAM [17], which have a resistance window of a few KΩ. Therefore, it is ideal for the proposed majority gate.…”

Section: B Sensing Methodologymentioning

confidence: 99%

“…To evaluate the number of gates that can be executed in parallel, we evaluated the area of the time-based SA. The time-based SA of [17] could sense the BL voltage without an op-amp, and, this was an important reason for adopting it for our majority gate (conventional SAs use operational amplifier, which consume huge silicon area). The layout of the timebased SA of Fig.3 is drawn in Fig.7 and occupies an area of 20 × 3 = 60 µm 2 .…”

Section: A Functional Completeness and Memory Controllermentioning

confidence: 99%

See 3 more Smart Citations

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

Reuben

Pechmann

2020

2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Efforts to combat the 'von Neumann bottleneck' have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it's expressive power. In this work, we propose a method to compute majority while reading from a transistoraccessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs' resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively. Index Terms-Resistive RAM (RRAM), majority logic, majority gate, memristor, 1 Transistor-1 Resistor(1T-1R), von Neumann bottleneck, in-memory computing, compute-in-memory, processing-in-memory, parallel-prefix adder This is author's version of the accepted paper. For the published paper, see the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) proceedings in https://ieeexplore.ieee.org/ See Conference presentation (20 min video) at https://asap2020.cs.manchester.ac.uk/paper.php?id=72

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Section: B Sensing Methodologymentioning

confidence: 98%

Section: B Sensing Methodologymentioning

confidence: 99%

Section: B Sensing Methodologymentioning

confidence: 99%

Section: A Functional Completeness and Memory Controllermentioning

confidence: 99%

See 2 more Smart Citations

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

Reuben

Pechmann

2020

2020 IEEE 31st International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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“…It must be noted that this will be exacerbated by the variability exhibited by the ReRAM devices. To meet this requirement, a time-based SA recently proposed in [33] was chosen and adapted to our requirement. Different from conventional sensing schemes (voltage-mode and current-mode), [33], which has a resistance margin of a few kΩ.…”

Section: B Sensing Methodologymentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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Emerging Memory Structures for VLSI Circuits

Garzón¹,

Yavits²,

Lanuzza³

et al. 2022

Wiley Encyclopedia of Electrical and Electronics Engineering

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Ever since the emergence of the electrical computer and the Von Neumann model, computer architects have adhered to a well‐structured hierarchy of memory solutions, clearly trading off performance and capacity with cost. The ubiquitous memory technologies, dominated by SRAM, DRAM, Flash, and magnetic hard disks, are each situated in a well‐defined location within this hierarchy. However, as processes have scaled into deep nanometer feature sizes and the demand for larger capacities and bandwidths increases, these traditional options face tough challenges and may be limited in their ability to continue to provide the new requirements. New technologies, such as phase change memory (PCM), magnetic RAM (MRAM), and resistive RAM (RRAM), have been researched and developed over the recent past in an attempt to meet these demands and replace some or all of the traditional technologies. In this article, the primary technologies are overviewed, including those that currently fill the memory hierarchy pyramid, the primary candidates to join or replace them in the near‐term, and a number of newer candidates that may arise as legitimate solutions in the farther term. In addition, an overview of the current state of processing within the emerging memory technologies is provided, as an attempt to break free of the traditional Von Neumann paradigm to overcome the energy and performance bottlenecks in modern systems.

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Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories

Cited by 28 publications

References 20 publications

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Emerging Memory Structures for VLSI Circuits

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