Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes

Panth, Shreepad; Samal, Sandeep Kumar; Samadi, Kambiz; Du, Yi; Lim, Sung Kyu

doi:10.1109/tcad.2017.2681064

Cited by 9 publications

(18 citation statements)

References 31 publications

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“…In M3D ICs, the two tiers are fabricated sequentially, while the conventional high-temperature annealing procedure can potentially cause damage to the transistors and copper interconnects on the other tier, and lead to performance degradation. Two methods have been proposed to mitigate this issue [20]: 1) utilize a low-temperature process on the top tier; 2) employee heat-tolerate material, such as tungsten, for the interconnects on the bottom tier. In our logic-on-memory 3D ICs, there are fewer signal interconnects on the bottom memory tier, while the standard-cell transistors on the top logic tier have much greater impact on the performance of the M3D IC.…”

Section: D Tier Degradation and Characterizationsmentioning

confidence: 99%

“…We now consider the performance degradation caused by M3D fabrication process in our implementation and analysis flow and mitigate the impacts with tungsten-based heterogeneous 3D interconnects. As described in Section IV-C, two methods have been proposed to mitigate this issue [20]: 1) utilize a low-temperature process on the top tier; 2) employee heattolerate material, such as tungsten, for the interconnects on the bottom tier. In our logic-on-memory 3D ICs, there are fewer signal interconnects on the bottom memory tier, while the standard-cell transistors on the top logic tier have a much greater impact on the performance of the M3D IC.…”

Section: A Reviewermentioning

confidence: 99%

“…Response: Thank you very much for the comment. We describe the procedure to characterize the interconnects and memory devices in Section IV-C. First, we characterize the parasitics of this heterogeneous BEOL stack based on the interconnect degradation model proposed in [20]. Using the same dimensions as the original BEOL stack in the 28-nm technology, we calculate the size-dependent resistivity for tungsten and regenerate the parasitic technology file using Cadence ® Quantus TM QRC.…”

Section: A Reviewermentioning

confidence: 99%

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High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors

Zhu

Bamberg

Pentapati

et al. 2021

IEEE Trans. VLSI Syst.

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Monolithic 3D IC (M3D) is a promising solution to improve the performance and energy-efficiency of modern processors. But, designers are faced with challenges in design tools and methodologies, especially for power and thermal verifications. We develop a new physical design flow that optimally places and routes cache modules in one tier and logic gates in the other. Our tool also builds high-quality clock and power delivery networks targeting logic-on-memory M3D designs. Lastly, we develop a sign-off analysis tool flow to evaluate power, performance, area (PPA), thermal, and voltage-drop quality for given M3D designs. Using our complete RTL-to-GDS tool flow, we design commercial quality 2D and M3D implementation of Arm Cortex-A7 and Cortex-A53 processors in a commercial 28nm technology. Experimental results show that our 3D processors offer 20% (A7) and 21% (A53) performance gain, compared with their 2D commercial counterparts. The voltage-drop degradation of our 3D Cortex-A7 and Cortex-A53 processors is less than 3% of the supply voltage, while temperature increase is 10.71°C and 13.04°C, respectively.

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Section: D Tier Degradation and Characterizationsmentioning

confidence: 99%

Section: A Reviewermentioning

confidence: 99%

Section: A Reviewermentioning

confidence: 99%

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High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors

Zhu

Bamberg

Pentapati

et al. 2021

IEEE Trans. VLSI Syst.

Self Cite

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“…Several works have explored the challenges associated with the M3D fabrication and manufacturing processes [11,22]. Due to high temperatures, sequential fabrication of the top tier over the bottom tier affects the quality of transistors and interconnects in the bottom tier during the ion implantation and thermal annealing processes.…”

Section: Related Workmentioning

confidence: 99%

“…However, state-of-the-art M3D integration faces technology-and fabrication-related challenges that negatively impact the performance of M3D circuits. The sequential integration of M3D requires a low-temperature top-tier annealing process to prevent any degradation in bottom-tier transistors [10,22] and alternative metals (e.g., tungsten) for the bottom-tier interconnects to withstand the high fabrication temperatures [11,22]. However, these decisions slow down the top-tier transistors and bottom-tier interconnects resulting in inter-tier process variations.…”

Section: Introductionmentioning

confidence: 99%

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

Chatterjee

Musavvir

Kim

et al. 2021

J. Emerg. Technol. Comput. Syst.

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Voltage/frequency island (VFI)-based power management is a popular methodology for designing energy-efficient manycore architectures without incurring significant performance overhead. However, monolithic 3D (M3D) integration has emerged as an enabling technology to design high-performance and energy-efficient circuits and systems. The smaller dimension of vertical monolithic inter-tier vias (MIVs) lowers effective wirelength and allows high integration density. However, sequential fabrication of M3D layers introduces inter-tier process variations that affect the performance of transistors and interconnects in different layers. Therefore, VFI-based power management in M3D manycore systems requires the consideration of inter-tier process variation effects. In this work, we present the design of an imitation learning (IL)-enabled VFI-based power-management strategy that considers the inter-tier process-variation effects in M3D manycore chips. We demonstrate that the IL-based power-management strategy can be fine-tuned based on the M3D characteristics. Our policy generates suitable V/F levels based on the computation and communication characteristics of the system for both process-oblivious and process-aware configurations. We show that the proposed process-variation-aware IL-based VFI implementation for M3D manycore chips lowers the overall energy-delay-product (EDP) by up to 16.2% on average compared to an ideal M3D system with no M3D process variations.

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Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective

2022

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Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes

Cited by 9 publications

References 31 publications

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective

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