Throughput and Power Efficiency Evaluation of Block Ciphers on Kepler and GCN GPUs Using Micro-Benchmark Analysis

Nishikawa, Naoki; Iwai, Keisuke; Tanaka, Hidema; Kurokawa, Takakazu

doi:10.1587/transinf.e97.d.1506

Cited by 11 publications

(1 citation statement)

References 13 publications

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“…Since T-tables are constant data and shared by all threads, they are a good candidate to store in the Shared Memory unit. Multiple studies on GPU implementations of AES have demonstrated the advantages of using the Shared Memory unit for storing T-tables [1,3,8,21,30,31,33], and our work adopts this implementation. To assign encryption tasks to GPU threads, we transform the AES encryption procedure into a single GPU kernel, where each GPU thread processes one block encryption, independently.…”

Section: Aes Encryptionmentioning

confidence: 99%

Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs

Jiang

Fei

Kaeli

2019

ACM Trans. Archit. Code Optim.

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To prevent information leakage during program execution, modern software cryptographic implementations target constant-time function, where the number of instructions executed remains the same when program inputs change. However, the underlying microarchitecture behaves differently when processing different data inputs, impacting the execution time of the same instructions. These differences in execution time can covertly leak confidential information through a timing channel. Given the recent reports of covert channels present on commercial microprocessors, a number of microarchitectural features on CPUs have been reexamined from a timing leakage perspective. Unfortunately, a similar microarchitectural evaluation of the potential attack surfaces on GPUs has not been adequately performed. Several prior work has considered a timing channel based on the behavior of a GPU's coalescing unit. In this article, we identify a second finer-grained microarchitectural timing channel, related to the banking structure of the GPU's Shared Memory. By considering the timing channel caused by Shared Memory bank conflicts, we have developed a differential timing attack that can compromise table-based cryptographic algorithms. We implement our timing attack on an Nvidia Kepler K40 GPU and successfully recover the complete 128-bit encryption key of an Advanced Encryption Standard (AES) GPU implementation using 900,000 timing samples. We also evaluate the scalability of our attack method by attacking an implementation of the AES encryption algorithm that fully occupies the compute resources of the GPU. We extend our timing analysis onto other Nvidia architectures: Maxwell, Pascal, Volta, and Turing GPUs. We also discuss countermeasures and experiment with a novel multi-key implementation, evaluating its resistance to our side-channel timing attack and its associated performance overhead. CCS Concepts: • Security and privacy → Hardware security implementation; Side-channel analysis and countermeasures; • Computer systems organization → Single instruction, multiple data;

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Section: Aes Encryptionmentioning

confidence: 99%

Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs

Jiang

Fei

Kaeli

2019

ACM Trans. Archit. Code Optim.

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Terabit encryption in a second: Performance evaluation of block ciphers in GPU with Kepler, Maxwell, and Pascal architectures

Lee

Goi

Phan

2018

Concurrency and Computation

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Summary With the emergence of IoT and cloud computing technologies, massive data are generated from various applications everyday and communicated through the Internet. Secure communication is essential to protect these data from malicious attacks. Block ciphers are one mechanism to offer such protection but unfortunately involve intensive computations that can be performance bottlenecks to the servers, especially when the data center needs to handle thousands of concurrent transactions. In this paper, we investigate the feasibility of the GPU as an accelerator to perform high‐speed encryption in server environments. We present optimized implementations of a conventional block cipher (AES) and new lightweight block ciphers (LEA, Chaskey, SIMON, SPECK, and SIMECK) across three new GPU architectures (Kepler, Maxwell, and Pascal). For AES, we improve the fine‐grain implementation by utilizing the warp shuffle instruction available in these three new GPU architectures, which yield a 6%‐16% improvement over the previous implementations. For LEA, Chaskey, SIMON, SPECK, and SIMECK, we first analyze why they cannot have efficient fine‐grain implementations in the GPU and then present our optimization techniques, which are able to achieve impressive encryption speeds of 1.912, 637, 1.485, 2.291, and 1.478 Tb/s, respectively, in GTX1080.

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