2005 6th International Conference on Electronic Packaging Technology
DOI: 10.1109/icept.2005.1564661
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Through wafer via technology for 3-D packaging

Feng Gao
1
,
Jian Cai
2
,
Shuidi Wang
3
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Cited by 5 publications
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Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

Jang
1
,
Ryu
2
,
Lee
3
et al. 2007
2007 Proceedings 57th Electronic Components and Technology Conference
129
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Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

Jang
1
,
Ryu
2
,
Lee
3
et al. 2007
2007 Proceedings 57th Electronic Components and Technology Conference
129
1
50
0
View full textAdd to dashboardCite

High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging

Ryu
1
,
Lee
2
,
Lee
3
et al. 2006
2006 1st Electronic Systemintegration Technology Conference
84
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29
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Laser drilled through silicon vias: Crystal defect analysis by synchrotron x-ray topography

Landgraf1,
Rieske
2
,
Danilewsky3
et al. 2008
2008 2nd Electronics Systemintegration Technology Conference
5
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4
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