Laser drilled through silicon vias: Crystal defect analysis by synchrotron x-ray topography

Landgraf, R.; Rieske, Ralf; Danilewsky, A.N.; Wolter, Klaus‐Jürgen

doi:10.1109/estc.2008.4684492

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…Laser ablation is an emerging low-cost and high-speed process for drilling TSV holes, as it benefits from the absence of any lithographic process steps and is agnostic to different materials. This results in high process and design flexibility and thus lower overall costs compared to DRIE [4,18]. Laser ablation, however, suffers from a high local thermal load, crystal defects and particle generation around the perimeter of the drilled via hole.…”

Section: Via Holesmentioning

confidence: 99%

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Wire-bonded through-silicon vias with low capacitive substrate coupling

Fischer

Grange

Roxhed

et al. 2011

J. Micromech. Microeng.

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Three-dimensional integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies with through-silicon vias (TSVs). They enable the realization of circuits with shorter signal path lengths, smaller packages and lower parasitic capacitances, which results in higher performance and lower costs. This paper presents a novel technique for fabricating TSVs from bonded gold wires. The wires are embedded in a polymer, which acts both as an electrical insulator, resulting in low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.

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Section: Via Holesmentioning

confidence: 99%

“…Laser ablation, however, suffers from a high local thermal load, crystal defects and particle generation around the perimeter of the drilled via hole. Additional cleaning steps are therefore required and reliability issues may arise due to induced stress on pores and micro-cracks [19,18].…”

Section: Via Holesmentioning

confidence: 99%

Wire-bonded through-silicon vias with low capacitive substrate coupling

Fischer

Grange

Roxhed

et al. 2011

J. Micromech. Microeng.

View full text Add to dashboard Cite

show abstract

“…Laser ablation is an emerging low-cost and high-speed process for drilling TSV holes as it benefits from the absence of any lithographic process steps and is agnostic to different materials. This results in high process and design flexibility and thus, potentially lower overall costs compared to DRIE [4,15]. Laser ablation however suffers from a high local thermal load, introduction of crystal defects and particle generation around the perimeter of the drilled via hole.…”

Section: Introductionmentioning

confidence: 99%

“…Laser ablation however suffers from a high local thermal load, introduction of crystal defects and particle generation around the perimeter of the drilled via hole. Additional cleaning steps are therefore required and reliability issues may arise due to induced stresses on pores and micro-cracks [15,16].…”

Section: Introductionmentioning

confidence: 99%

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Fischer

Bleiker

Somjit

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (> 8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications. IntroductionDuring the past decades, hybrid integration of IC and MEMS technology has been dominated by 2-D approaches, resulting in Multi-Chip Modules (MCM) where different dies are integrated on a single substrate, and System-on-Chip (SoC) solutions where different functionalities are merged onto one die. CMOS and MEMS processing are both well-established and cost-efficient base technologies that are characterized by short development times, low fabrication costs and high yields. Separate manufacturing of CMOS integrated circuit dies and MEMS dies and their subsequent integration into a System-in-Package (SiP) offers high versatility and low process costs, and thus is an attractive alternative to SoC solutions. Especially 3D-integrated System in Package (3D-SiP) solutions, which are based on vertical chip stacking, are a general trend in many integration approaches. Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1,2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3]. 3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors and microphones, CMOS imagers and power LEDs successfully incorporate TSV technology [4][5][6].

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