Wire-bonded through-silicon vias with low capacitive substrate coupling

Fischer, Andreas; Grange, Matthew; Roxhed, Niclas; Weerasekera, Roshan; Pamunuwa, Dinesh; Stemme, G.; Niklaus, Frank

doi:10.1088/0960-1317/21/8/085035

Cited by 19 publications

(22 citation statements)

References 23 publications

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“…This concept is however limited to comparable low aspect ratios on the order of 1.5 : 1 [131]. In order to realize TSVs with higher aspect ratios (up to 20 : 1) another concept has been implemented by Schröder et al [132].…”

Section: A) B)mentioning

confidence: 99%

“…Through silicon via (TSV) concepts based on wire bonding technology: a) Conceptual CAD image of a wire-bonded through-silicon via with low capacitive substrate coupling. b) SEM image of the conductive core of the via, which consists of a gold wire that has been wire-bonded on a metal membrane on the bottom of the cavity [131]. c) Conceptual CAD image of a wire-bonded through-silicon via with high aspect ratios.…”

Section: A) B)mentioning

confidence: 99%

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Unconventional applications of wire bonding create opportunities for microsystem integration

Fischer

Korvink

Roxhed

et al. 2013

J. Micromech. Microeng.

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, G. et al. (2013) "Unconventional applications of wire bonding create opportunities for microsystem integration" Journal of Micromechanics and Microengineering, 23(8) Abstract. Automatic wire bonding is a highly mature, cost-efficient and broadly available back-end process, intended to create electrical interconnections in semiconductor chip packaging. Modern production wire bonding tools can bond wires with speeds of up to 30 bonds per second with placement accuracies of better than 2 µm, and the ability to form each wire individually into a desired shape. These features render wire bonding a versatile tool also for integrating wires in applications other than electrical interconnections. Wire bonding has been adapted and used to implement a variety of innovative microstructures. This paper reviews unconventional uses and applications of wire bonding that have been reported in the literature. The used wire bonding techniques and materials are discussed, and the implemented applications are presented. They include the realization and integration of coils, transformers, inductors, antennas, electrodes, through silicon vias (TSVs), plugs, liquid and vacuum seals, plastic fibers, shape memory alloy (SMA) actuators, energy harvesters, and sensors.

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Section: A) B)mentioning

confidence: 99%

Section: A) B)mentioning

confidence: 99%

Unconventional applications of wire bonding create opportunities for microsystem integration

Fischer

Korvink

Roxhed

et al. 2013

J. Micromech. Microeng.

Self Cite

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“…Typical TSV diameters vary between a few microns [2,7] and several hundreds of microns [8,9]. Basic via designs are either based on solid or lined metallizations for the vertical conductor.…”

Section: Introductionmentioning

confidence: 99%

“…Basic via designs are either based on solid or lined metallizations for the vertical conductor. TSVs can have either straight [7][8][9][10][11] or tapered sidewall profiles [12,13] as well as combinations of both [1,14]. Various methods for the formation of via holes exist and can be categorized into dry etching [1,7,8,[10][11][12][13][14], wet etching [14] and drilling processes [4].…”

Section: Introductionmentioning

confidence: 99%

“…The use of organic dielectrics such as Benzocyclobutene (BCB) [9,13,17], epoxy-based polymers [8,13], silicone [13] or Parylene [11] is also considered as viable option. Polymers, especially low-k types with a lower relative permittivity compared to silicon dioxide, are very attractive for the realization of TSVs with improved electrical characteristics [8].…”

Section: Introductionmentioning

confidence: 99%

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High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Fischer

Bleiker

Somjit

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (> 8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications. IntroductionDuring the past decades, hybrid integration of IC and MEMS technology has been dominated by 2-D approaches, resulting in Multi-Chip Modules (MCM) where different dies are integrated on a single substrate, and System-on-Chip (SoC) solutions where different functionalities are merged onto one die. CMOS and MEMS processing are both well-established and cost-efficient base technologies that are characterized by short development times, low fabrication costs and high yields. Separate manufacturing of CMOS integrated circuit dies and MEMS dies and their subsequent integration into a System-in-Package (SiP) offers high versatility and low process costs, and thus is an attractive alternative to SoC solutions. Especially 3D-integrated System in Package (3D-SiP) solutions, which are based on vertical chip stacking, are a general trend in many integration approaches. Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1,2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3]. 3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors and microphones, CMOS imagers and power LEDs successfully incorporate TSV technology [4][5][6].

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Esashi

2021

3D and Circuit Integration of MEMS

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Wire-bonded through-silicon vias with low capacitive substrate coupling

Cited by 19 publications

References 23 publications

Unconventional applications of wire bonding create opportunities for microsystem integration

Unconventional applications of wire bonding create opportunities for microsystem integration

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

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