Through wafer interconnects on active pMOS devices

Johnson, V.N.; Jozwiak, J.; Moll, Amy

doi:10.1109/wmed.2004.1297358

Cited by 5 publications

(4 citation statements)

References 2 publications

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“…technology [15] compared to the bulk approach [16]. This is primarily due to low substrate thickness in SOI and hence, for a given aspect ratio, smaller TSV diameters and therefore smaller pitches can be used in 3D SOI technology.…”

Section: D Integration Technologiesmentioning

confidence: 99%

Robust signaling techniques for through silicon via bundles

Chillara

Jang

Burleson

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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Section: D Integration Technologiesmentioning

confidence: 99%

Robust signaling techniques for through silicon via bundles

Chillara

Jang

Burleson

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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“…There have been several reports of silicon or glass wafer-through-patterned methods. However, most of the silicon through-patterning techniques are applied to the interconnection of devices [12][13][14][15][16][17][18][19][20]. Johnson et al [13] showed through-wafer interconnects for p-type metal-oxidesemiconductor field-effect transistor (pMOS) devices and Wang et al [14] showed through-wafer interconnects for waferlevel hermetic packages.…”

Section: Introductionmentioning

confidence: 99%

“…However, most of the silicon through-patterning techniques are applied to the interconnection of devices [12][13][14][15][16][17][18][19][20]. Johnson et al [13] showed through-wafer interconnects for p-type metal-oxidesemiconductor field-effect transistor (pMOS) devices and Wang et al [14] showed through-wafer interconnects for waferlevel hermetic packages. Abe et al [15] showed electrical interconnections using laser-drilled glass wafers, but they used through-holes as interconnects.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

Kim¹,

Kim²

2009

J. Micromech. Microeng.

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We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m −2 at 60-180 • C for the dry film resist and 0.4-1.9 J m −2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

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“…During the passivation cycle, a thin coating of Teflon-like polymer also deposits on these silicon grass structures, and that further reduce the silicon etch rate and promotes the formation of grass-like structures. etched in 400 µm thick silicon wafer (aspect ratio ~7) [100]. The coil and platen power are 800 W, and 14 W, respectively while the average etch rate is 3µm/min.…”

Section: Micro-masking (Bottom Silicon Grass Formation)mentioning

confidence: 99%

Fabrication & characterization of high aspect ratio fine pitch deep reactive ion etched through-wafer electroplated copper interconnects

Dixit¹

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, for providing their full support. • To my childhood friends Waseem Ahmed, Manish Tiwari, Alok Yadav, Goverdhan Dobhal, my brother Sandeep Dixit and sister Shalini Dixit and many others for their friendly support and advice. Finally my special gratitude is towards my parents and family, for their love, encouragement and support throughout my research duration. Without my parents, I would not have learnt the meaning of working hard. By creating the opportunities for me to have a good education, they have provided me the best possible thing, I could have ever wished for. To them, I am eternally grateful. Special thanks and appreciation are to my girl friend Zhao Jin, for standing besides me during the tough time. Her encouragement and selfless support has motivated me to achieve success in completing this research work. I would also like to thank her parents Liu Huamin and Zhao Anmin for their continuous trust and support.

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Through wafer interconnects on active pMOS devices

Cited by 5 publications

References 2 publications

Robust signaling techniques for through silicon via bundles

Robust signaling techniques for through silicon via bundles

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

Fabrication & characterization of high aspect ratio fine pitch deep reactive ion etched through-wafer electroplated copper interconnects

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