Through the Looking Glass-2020 Edition: Trends in Solid-State Circuits From ISSCC

Daly, Denis C.; Fujino, Laura Chizuko; Smith, K.C.

doi:10.1109/mssc.2019.2952282

Cited by 19 publications

(4 citation statements)

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“…Several of these impairments will be more challenging for localization and sensing than for communication, as the latter relies on the end-to-end radio channel, while the former must consider each impairment separately to understand the impact on estimation of delays, angles, and Dopplers. The increased data rate will require higher clock speed, higher bandwidth [55] and potentially more energy consumption in digital modems. Therefore, the usability and potential of upper mmWave and THz bands will heavily rely on the current and future development of semiconductor technologies.…”

Section: A Extreme Radio Performancementioning

confidence: 99%

6G Vision, Value, Use Cases and Technologies From European 6G Flagship Project Hexa-X

Uusitalo¹,

et al. 2021

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Section: A Extreme Radio Performancementioning

confidence: 99%

6G Vision, Value, Use Cases and Technologies From European 6G Flagship Project Hexa-X

Uusitalo¹,

et al. 2021

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“…The data rates of wireline links are trending to double every four years [18]. As the data-rate-per-lane increases, the skin effect and dielectric losses in a conductor-based channel intensify and cause high-frequency signal loss.…”

Section: Wireline Interface Overviewmentioning

confidence: 99%

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators

Lee

Kim

Park

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In convolutional neural network (CNN) accelerators, the dominant power consumption is caused by the access of external data memory. In addition, power and area occupied by I/O interfaces maintaining low bit-error-rate, e.g., 1e-15, grow as the data rate increases. Considering the inherent error resilience of the inference process in machine learning applications, the requirement of error-free communication in the data-path is controversial. In this paper, a custom CNN accelerator integrating a channel emulator is designed by using an FPGA to analyze the effect of the BER of an I/O transceiver on the image classification accuracy. In order to implement a channel emulator, a digital-domain look-up-table (LUT)-based 12-tap FIR filter is employed to create inter-symbol interference (ISI), and a PRBS31 generator is used as a noise source. The implementation was evaluated by running the ImageNet dataset on the FPGA-based custom accelerator (Virtex Ultrascale+) implementing VGG-16. The results show that the BER up to 1e-4 in the memory access has a negligible impact on the inference accuracy.

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“…Typically, deep neural network (DNN) tasks run on GPUs or FPGAs devices in data centers, characterized by a power envelope that is orders of magnitude higher than what is sustainable on extreme-edge devices. Dedicated DNN accelerators are starting to gain traction for ultra-low power devices [6], [7], but they require extra silicon area, which is often not affordable in the extremely cost-conscious and fragmented IoT market. On the other hand, resource-constrained MCUs are the standard computing platforms used to build extreme-edge nodes, thanks to their flexible software programmability, low-cost and low-power characteristics.…”

Section: Introductionmentioning

confidence: 99%

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes

Garofalo

Tagliavini

Conti

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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Strongly quantized fixed-point arithmetic is now considered a well-established solution to deploy Convolutional Neural Networks (CNNs) on limited-memory low-power IoT endnodes. Such a trend is challenging due to the lack of support for low bitwidth fixed-point instructions in the Instruction Set Architecture (ISA) of state-of-the-art embedded Microcontrollers (MCUs), which are mainly based on closed ISA such as ARM Thumb2 and associated Helium extensions. Emerging opensource ISAs such as RISC-V provide a flexible way to address this challenge. This work introduces lightweight extensions to the RISC-V ISA to boost the efficiency of heavily Quantized Neural Network (QNN) inference on microcontroller-class cores.By extending the ISA with nibble (4-bit) and crumb (2-bit) SIMD instructions, we are able to show near-linear speedup with respect to higher precision integer computation on the key kernels for QNN computation. Also, we propose a custom execution paradigm for SIMD sum-of-dot-product operations, which consists of fusing a dot product with a load operation, with an up to 1.64 × peak MAC/cycle improvement compared to a standard execution scenario. To further push the efficiency, we integrate the RISC-V extended core in a parallel cluster of 8 processors, with near-linear improvement with respect to a single core architecture. To evaluate the proposed extensions, we fully implement the cluster of processors in GF22FDX technology. QNN convolution kernels on a parallel cluster implementing the proposed extension run 6 × and 8 × faster when considering 4-and 2-bit data operands, respectively, compared to a baseline processing cluster only supporting 8-bit SIMD instructions. With a peak of 2.22 TOPs/s/W, the proposed solution achieves efficiency levels comparable with dedicated DNN inference accelerators, and up to three orders of magnitude better than state-of-theart ARM Cortex-M based microcontroller systems such as the low-end STM32L4 MCU and the high-end STM32H7 MCU.

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Through the Looking Glass-2020 Edition: Trends in Solid-State Circuits From ISSCC

Cited by 19 publications

References 0 publications

6G Vision, Value, Use Cases and Technologies From European 6G Flagship Project Hexa-X

6G Vision, Value, Use Cases and Technologies From European 6G Flagship Project Hexa-X

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes

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