Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results

Henry, David D.; Charbonnier, Jean; Chausse, P.; Jacquet, F.; Aventurier, Bernard; Brunet-Manquat, C.; Lapras, V.; Anciant, R.; Sillon, N.; Dunne, B.; Hotellier, N.; Michailos, Jean

doi:10.1109/eptc.2008.4763409

Cited by 27 publications

(7 citation statements)

References 3 publications

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“…Specifically, the digital focal plane storage permits a straightforward use of the image sensor as an image frame buffer when incorporated as part of a vertically-integrated system. In this potential system, our image sensor might be massively connected to the image processor by using, for instance, Through Silicon Vias (TSV) [49]. Thus, the die (or tier, as they are typically known on 3-D technologies) on top might contain our design, whereas the die underneath might contain a digital processor, standardized I/Os, third-party DSP blocks, etc.…”

Section: Discussion Of Resultsmentioning

confidence: 99%

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

2015

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This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone mapping algorithm during image capture operation. The histogram of the previous frame of an auxiliary image, which contains time stamp information, is employed as an estimation of the probability of illuminations impinging pixels at the present frame. The compression function of illuminations, namely tone mapping curve, is calculated using this histogram. A QCIF resolution proof-of-concept prototype has been fabricated using a 0.35 µm opto-flavored standard technology. The sensor is capable of mapping scenes with a maximum intra-frame dynamic range of 151 dB (25 bits/pixel in linear representation) by compressing them to only 7 bits/pixel, while keeping visual quality in details and contrast. The in-pixel on-the-fly fully parallel tone mapping achieves high-frame rate allowing real-time high dynamic range video (120 dB at 30 frames/s).Index Terms-CMOS image sensor, high dynamic range, tone mapping, pulse width modulation, real-time HDR video.

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Section: Discussion Of Resultsmentioning

confidence: 99%

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

2015

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“…More details can be found in previous publications [7,8]. The post-process for via-last technology included the following main technological steps:…”

Section: General Process Descriptionmentioning

confidence: 99%

“…As the 1:1-aspect-ratio TSV process has been firstly developed for wafer-level packaging using permanent BCB bonding for CMOS image sensors [7,8], we decided to assess the 1:1 TSV creation on ST Microelectronics CMOS Image Sensor (CIS) wafers using a temporary bonding process.…”

Section: General Process Descriptionmentioning

confidence: 99%

Integration of a temporary carrier in a TSV process flow

Charbonnier

Chéramy

Henry

et al. 2009

2009 59th Electronic Components and Technology Conference

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wafer stacking technologies offer new possibilities in terms of device architecture and miniaturization [1][2][3]. To stack wafers, reliable throughsilicon vias (TSVs) and interconnections must be processed into ultrathin wafers, and such processing is made possible by new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives can offer a variety of properties sufficient for withstanding the TSV processes: flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning processes. This paper demonstrates that, contrary to tapes and waxes currently used for temporary bonding, a new removable high-temperature adhesive  meets all the requirements named above for reliable TSV processing on 8-inch active wafers. We will first describe formation of TSVs with aspect ratios of 1:1 and 2:1 into thinned wafers. IntroductionTo be successful, 3-D ultrathin wafer stacking technologies require the development of reliable through-die interconnects with varying aspect ratios depending on the application. This type of integration poses forward new challenges in the development of new TSV processes suitable for thin-wafer handling technologies.It has already been demonstrated in a previous publication [4] that a temporary bonding process using new hightemperature adhesives  could provide an innovative and robust solution to produce functional 1:1 aspect ratio TSVs in 70-micron-thick silicon wafers. This first result showed that in addition to presenting sufficient thermal and mechanical properties to withstand all the backside process steps, the high-temperature adhesive enables easy bonding, debonding, and cleaning processes.Although encouraging, these first results obtained on plain silicon wafers were not completely representative of TSV integration in industrial products. Indeed, due to the presence of several metallization and passivation layers, an active CMOS-containing wafer can present a different deformation behavior compared to a plain wafer when heated, which can weaken its adhesion to the temporary layer during the process. Therefore the purpose of this paper is to assess the TSV creation on temporarily bonded complex active wafers.In the first part of this paper, we will assess the full TSV realization on device wafers thinned to 70 microns thanks to a temporary bonding process. The active wafers used were

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“…The imager wafer is permanently bonded to a glass wafer that will act as mechanical carrier as well as an optical part of the future device, as it is done in wafer-level packaged sensors [4]. Bonding is performed with a 7 µm thick SiNR adhesive layer, patterned in a lace around the pixel array ( Figure 13).…”

Section: ) Permanent Bonding and Wafer Thinningmentioning

confidence: 99%

“…Among an extensive list of potential applications, the Wafer Level Packaging of CMOS Image Sensors (CIS) for mobile phones became the first industrial scenario using such a vertical approach [4]. This technology, based on the so-called Through Silicon Via (TSV) in a via-last approach, is now routinely used in production with high yield and robust reliability.…”

Section: Introductionmentioning

confidence: 99%

3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

Coudrain

Henry²,

Berthelot³

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.

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Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results

Cited by 27 publications

References 3 publications

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

Integration of a temporary carrier in a TSV process flow

3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

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