Through Recess and Regrowth Gate Technology for Realizing Process Stability of GaN-Based Gate Injection Transistors

Okita, Hideyuki; Hikita, Masahiro; Nishio, Akihiko; Satô, Takahiro; Matsunaga, Keiichi; Matsuo, Hideaki; Tsuda, Michinobu; Mannoh, M.; Kaneko, Saichiro; Kuroda, Masayuki; Yanagihara, Manabu; Ikoshi, Ayanori; Morita, Tatsuo; Tanaka, Kenichiro; Uemoto, Yasuhiro

doi:10.1109/ted.2017.2653847

Cited by 22 publications

(8 citation statements)

References 5 publications

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“…Parasitic contact resistance ( R C ) is one of the major limiting factors of the device performance as the device dimensionality decreases. ,, A low parasitic R C is crucial for low-power and high-frequency operation. A doped cap layer can generally be formed to lower the parasitic R C ; however, its formation involves a trade-off with the on/off output current ratio. , Recess technology, which involves the usage of a doped cap layer and channel etching, has been extensively studied for AlGaN/GaN and AlGaAs/GaAs high-electron-mobility transistors. − Selective and damage-free etching in the channel (or gate) is essential for achieving good electrostatic controllability. Nonlithographic recess-channel fabrication methods have been applied to a 2D material-based device, yielding a scalable top-down FET with good channel controllability. , In the self-alignment process, existing electrodes or patterns are employed as masks for the subsequent steps, and an additional photolithography process is not required.…”

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confidence: 99%

Recessed-Channel WSe₂ Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

et al. 2022

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Effective channel control with low contact resistance can be accomplished through selective ion implantation in Si and III–V semiconductor technologies; however, this approach cannot be adopted for ultrathin van der Waals materials. Herein, we demonstrate a self-aligned fabrication process based on self-terminated p-doping and layer-by-layer chemical etching to achieve low contact resistance as well as a high on/off current ratio in ultrathin tungsten diselenide (WSe2) field-effect transistors (FETs). Damage-free layer-by-layer thinning of the WSe2 channel is repeated up to a thickness of approximately 1.4 nm, while maintaining the selectively p-doped source/drain regions. The device characteristics of the recessed-channel WSe2 FET are systematically monitored during this layer-by-layer recess-channel process. The WSe2 etching rate is estimated to be 2–3 layers per cycle of oxidation and subsequent chemical etching. The self-terminated tungsten oxide (WOX) layer grown through ultraviolet–ozone treatment induces robust p-doping in the neighboring (or underlying) WSe2 through the electron withdrawal mechanism, which remains in the source/drain regions after channel oxide removal. The adopted self-terminated and self-aligned recess-channel process for ultrathin WSe2 FETs enables the realization of a high on/off output current ratio (>108) and field-effect mobility (∼190 cm2/V·s), while maintaining low contact resistance (0.9–6.1 kΩ·μm) without a postannealing process. The proposed facile and reproducible doping and atomic-layer-etching method for the fabrication of a recessed-channel FET with an ultrathin body can be helpful for high-performance two-dimensional semiconductor devices and is applicable to post-Si complementary metal-oxide semiconductor devices.

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confidence: 99%

Recessed-Channel WSe₂ Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

et al. 2022

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“…The hole removal is inefficient through either the gate stack or the substrate, due to the larger-bandgap AlGaN or AlN in the heterostructures or transition layers. Even in the gate injection transistor, which is known for the viability of hole injection from the p-GaN gate, 67) the thin AlGaN barrier in the gate stack 68) could still block the hole removal. This inefficient hole removal prevents the avalanche breakdown; the hole accumulation below the gate stack leads to the gate barrier lowering 64) and E-field crowding, making the device suffer from a destructive breakdown.…”

Section: Non-avalanche Breakdownmentioning

confidence: 99%

Power device breakdown mechanism and characterization: review and perspective

Zhang

2023

Jpn. J. Appl. Phys.

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Breakdown voltage (BV) is arguably one of the most critical parameters for power devices. While avalanche breakdown is prevailing in silicon and silicon carbide devices, it is lacking in many wide bandgap (WBG) and ultra-wide bandgap (UWBG) devices, such as the gallium nitride high electron mobility transistor, due to the deployment of junction-less device structures or the inherent material challenges of forming p-n junctions. This paper starts with a survey of avalanche and non-avalanche breakdown mechanisms, followed by the distinction between the static and dynamic BV. Various BV characterization methods, including the static and pulse I-V sweep, unclamped and clamped inductive switching, as well as continuous overvoltage switching, are comparatively introduced. The device physics behind the time- and frequency-dependent BV as well as the enabling device structures for avalanche breakdown are also discussed. The paper concludes by identifying research gaps for understanding the breakdown of WBG and UWBG power devices.

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“…Normally-off AlGaN/GaN heterostructure field-effect transistors (HFETs) have attracted much attention for power switching applications because of their inherent fail-safe property, simple circuit configuration and high electron mobility of two-dimensional electron gas (2DEG). [1][2][3] Generally, a threshold voltage (V th ) higher than 3.0 V as well as a gate voltage swing of 10 V are desirable to avoid the malfunction caused by noise. [4] For some special power switching applications, a V th of 6.0 V is desired to prevent the power switches from faulty turn-on induced by the electromagnetic interference.…”

Section: Introductionmentioning

confidence: 99%

Normally-off AlGaN/GaN heterojunction field-effect transistors with in-situ AlN gate insulator

Pu¹,

Li²,

Wang³

et al. 2022

Chinese Phys. B

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In this study, AlGaN/GaN heterojunction field-effect transistors (HFETs) with p-GaN cap layer are developed for normally-off operation, in which an in-situ grown AlN layer is utilized as gate insulator. Compared with the SiNx gate insulator, the AlN/p-GaN interface presents a more obvious energy band bending and a wider depletion region, which helps to positively shift the threshold voltage. In addition, the relatively large conduction band offset of AlN/p-GaN is beneficial to suppress the gate leakage current and enhance the gate breakdown voltage. Owing to the introduction of AlN layer, normally-off p-GaN capped AlGaN/GaN HFET with a threshold voltage of 4 V and a gate swing of 13 V is realized. Furthermore, the field-effect mobility is approximately 1500 cm2V-1s-1 in 2DEG channel, implying the good device performance.

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Through Recess and Regrowth Gate Technology for Realizing Process Stability of GaN-Based Gate Injection Transistors

Cited by 22 publications

References 5 publications

Recessed-Channel WSe₂ Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

Recessed-Channel WSe₂ Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

Power device breakdown mechanism and characterization: review and perspective

Normally-off AlGaN/GaN heterojunction field-effect transistors with in-situ AlN gate insulator

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Through Recess and Regrowth Gate Technology for Realizing Process Stability of GaN-Based Gate Injection Transistors

Cited by 22 publications

References 5 publications

Recessed-Channel WSe2 Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

Recessed-Channel WSe2 Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

Power device breakdown mechanism and characterization: review and perspective

Normally-off AlGaN/GaN heterojunction field-effect transistors with in-situ AlN gate insulator

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Product

Resources

About

Recessed-Channel WSe₂ Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching

Recessed-Channel WSe₂ Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching