Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors

Abstract

In this paper, a two dimensional analytical model of the threshold voltage for HGD TFET structure has been proposed. We have also presented the analytical models for the tunneling width and the channel potential. The potential model is used to develop the physics based model of threshold voltage by exploring the transition between linear to exponential dependence of drain current on the gate bias. The proposed model depends on the drain voltage, gate dielectric near the source and drain, silicon film thickness, work function of gate metal and oxide thickness. The accuracy of the proposed model is verified by simulation results of 2-D ATLAS simulator. Due to the reduction of the equivalent oxide thickness, the coupling between the gate and the channel junction enhances which results in lower threshold voltage. Tunneling width becomes narrower at a given gate voltage for the optimum channel concentration of 1016 /cm3. The higher concentration in the source (Ns) causes a steep bending in the conduction and valence bands compared to the lower concentration which results in smaller tunneling width at the source-channel interface.

Drain Current Model for a Single Gate Tunnel Field Effect Transistor with Hetero-Dielectric Gate (HDG)

“…Following the same procedure, as mentioned in our earlier paper [40], differential equation (1) can be reduced to 2-D scaling equation,…”

“…Where, a0, aj1, aj2 are constants and function of x-only. The value of these unknowns can be obtained by using appropriate Boundary Conditions (BCs) [40].…”

“…Where, Na is the channel doping concentration, j=1, 2 represents the region I and region II, εsi is the silicon permittivity, ψj(x,y) is the 2-D electrostatic potential in the region I and II measured with respect to Fermi potential. Solution of this differential equation ( 1) can be obtained by assuming parabolic profile along the film thickness tsi as [40];…”

“…Far fast circuit simulation and to provide in depth understanding of the working principle of the HDG TFET, it is required to develop an analytical compact models. In the literature, various analytical models were proposed [35][36][37][38][39][40] but these models are either based on iterative methods or many assumptions. However, no compact closed form of drain current analytical expression of single gate HDG TFET structure is available in the literature.…”

Drain current model for a hetero‐dielectric single gate tunnel field effect transistor (HDSG TFET)

“…But models presented in literature are either based on iterative methods or several assumptions. [37][38][39][40][41][42] However, no compact closed form of drain current analytical expression is available in the literature for a single gate hetero dielectric TFET.…”