Threshold Read Method for Multi-bit Memristive Crossbar Memory

Yilmaz, Yalcin; Mazumder, Pinaki

doi:10.1109/ised.2011.68

Cited by 5 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [29] the authors proposed a solution for decoding multi-bit memristive states, in which the intermediate node is connected to a series of diodes. Each diode in this chain contributes a certain bias level.…”

Section: Encoding and Decoding Of Multi-bit Memristive Statesmentioning

confidence: 99%

“…Therefore, the possible area overhead in the periphery is perhaps something to consider seriously in large multi-level crossbar arrays. On the other hand, the conversion circuit which uses active elements, proposed in [29], reduces the number of necessary comparators by half; hence it could be instead a more attractive design option.…”

Section: Encoding and Decoding Of Multi-bit Memristive Statesmentioning

confidence: 99%

See 1 more Smart Citation

High-Radix Arithmetic-Logic Unit (ALU) Based on Memristors

Vourkas

Sirakoulis

2015

Emergence, Complexity and Computation

View full text Add to dashboard Cite

It is well-known that faster arithmetic operations could be achieved via high-radix numeric systems [1]. However, due to the absence of appropriate storage devices, such a practice was not given much attention so far because it would require memory capacity doubling in order to represent high-radix numbers in binary mode. Moreover, in view of the prospected end of the so called "Moore's law", many new approaches, which aim to extend the applicability of Complementary Metal-Oxide-Semiconductor (CMOS)-based circuits and systems, have been proposed by the semiconductor industry. In fact, Flash memory is approaching fundamental scaling limits due to several reliability issues. Therefore, currently there is a growing interest in new devices for information processing and memory, as well as new technologies and paradigms for system architecture [2][3][4][5][6][7][8][9]. An exciting approach would be the development of a competitive, reliable, multi-level storage cell technology, which will enable storing multiple bits of information in a single memory element [10,11]. Most such approaches so far are based on transistors [2], but the recent discovery of the memristor has renewed the interest for this promising scientific area [12][13][14]. Owing to their analog nature, memristors have a remarkable ability to store multi-bit values in a single cell [15,16]; a property which adds significantly to their potential use in future multi-level storage cell technologies and high-radix arithmetic units [17].Nowadays, there is a notable variety of systems that exhibit memristive behavior [18]. As it was also mentioned in the previous chapters, memristors offer several advantages, such as nonvolatility, rapid switching, low power consumption, and compatibility with conventional CMOS technology. Additionally, they provide an unconventional computation framework, which combines information processing and storage in the memory cell itself; the major distinction from the present computing paradigms [19,20]. Such favorable performance characteristics render them a candidate technology, able to bring the next technological revolution in electronics,

show abstract

Section: Encoding and Decoding Of Multi-bit Memristive Statesmentioning

confidence: 99%

Section: Encoding and Decoding Of Multi-bit Memristive Statesmentioning

confidence: 99%

High-Radix Arithmetic-Logic Unit (ALU) Based on Memristors

Vourkas

Sirakoulis

2015

Emergence, Complexity and Computation

View full text Add to dashboard Cite

show abstract

“…Finally these signals have to be converted according to the selected coding scheme for an SD (see table 1). Yilmaz and Prazunder presented in [22] a solution for the decoding of multi-bit memristive states in which the intermediate node is connected to a serial chain of active diode elements. Each diode in this chain contributes a certain bias level.…”

Section: Connecting Memristor Register Model With Sd Adder Transistor...mentioning

confidence: 99%

“…During downward traversing equation ( 21), which has a delay time of Δ 2 , is repeated − log n ( ( ) 1) times (downward traversing requires one gate delay less than upward traversing). A further Δ 3 is necessary for (22) and another Δ 3 for twoʼs complement formation. This results in a total run time of Δ + log n (4 ( ) 5) .…”

Section: Estimation Of Time and Area Effort For Ripple-carry-addermentioning

confidence: 99%

See 1 more Smart Citation

Using the multi-bit feature of memristors for register files in signed-digit arithmetic units

Fey

2014

Semicond. Sci. Technol.

View full text Add to dashboard Cite

One of the outstanding features of memristors is their principle possibility to store more than one binary value in a single memory cell. Due to their further benefits of non-volatility, fast access times, low energy consumption, compactness and compatibility with CMOS logic, memristors are excellent devices for storing register values nearby arithmetic units. In particular, the capability to store multi-bit values allows one to realise procedures for high-speed arithmetic circuits, which are not based on usual binary but on ternary values. Arithmetic units based on three-state number representation allow carrying out an addition in two steps, i.e., in O (1), independent of the operands word length n. They have been well-known in literature for a long time but have not been brought into practice because of the lack of appropriate devices to store more than two states in one elementary register or main memory cell. The disadvantage of this number representation is that a corresponding arithmetic unit would require a doubling of the memory capacity. Using memristors for the registers can avoid this drawback. Therefore, this paper presents a conceptual solution for a three-state adder based on tri-stable memristive devices. The principal feasibility of such a unit is demonstrated by SPICE simulations and the performance increase is evaluated in comparison with a ripple-carry and a carry-look-ahead adder.

show abstract