Three engines to solve verification constraints of decimal Floating-Point operation

Sayed-Ahmed, Amr; Fahmy, Hossam A. H.; Hassan, Mahmoud Y.

doi:10.1109/acssc.2010.5757585

Cited by 11 publications

(9 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One advantage of the proposed algorithm, is that it does not require bit level analysis or creating Cartesian equations and developing a particular engine to solve these equations as in [2], [3], [5], [10], [11]. Our constraints are word level constraints and are applied on existing SV constraint solvers.…”

Section: Evaluation Resultsmentioning

confidence: 99%

“…This is basically the internal algorithm of FPgen tool that the author develops to verify addition, subtraction, multiplication and division. [10] and [11] use similar approach by creating their own engines to solve simultaneously constraints on unbounded intermediate results and constraints on inputs-outputs. This methodology has proven effectiveness in verifying AdditionSubtraction, Multiplication and Fused Multiply Add operations for Decimal FP units.…”

Section: Introductionmentioning

confidence: 98%

See 1 more Smart Citation

Binary floating point verification using random test vector generation based on SV constraints

Nouh

Fahmy

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

Self Cite

View full text Add to dashboard Cite

Verification of Binary Floating Point (FP) Arithmetic requires robust techniques to prove compliance with Floating point IEEE Standard (IEEE Std 754-2008). This paper provides a new verification methodology that uses a constraint based random technique to generate test vectors for validating FP arithmetic instructions. The new proposal is generic and can be used to verify any software or hardware binary FP design. The constraints used in verification are written in System Verilog (SV) language and can be solved with any SV constraint solver tool. The paper provides a case study to prove the feasibility and usefulness of the proposed approach in finding bugs for Addition-Subtraction and Multiplication operations.

show abstract

Section: Evaluation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Binary floating point verification using random test vector generation based on SV constraints

Nouh

Fahmy

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…The freely available test vectors from Cairo University [82] were successful also in detecting errors in various designs [51,67,83] as well as in software libraries.…”

Section: Verificationmentioning

confidence: 99%

Decimal Floating Point Number System

Fahmy

2017

Embedded Systems Design With Special Arithmetic and Number Systems

Self Cite

View full text Add to dashboard Cite

“…Cairo University in cooperation with SilMinds developed an alternative engine. This verification work [21] included a DFP set of models compliant with the IEEE 754-2008 standard and a model-based test case generator with the same format as IBM's. We built a free tool [22] to parse the test cases generated from either Cairo University or IBM to produce output files with test vectors suitable for direct use with hardware simulators.…”

Section: Dfp Hardware Unitsmentioning

confidence: 99%

Decimal Floating Point for future processors

Fahmy

ElDeeb²,

Hassan³

et al. 2010

2010 International Conference on Microelectronics

Self Cite

View full text Add to dashboard Cite

Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fusedmultiply-add compliant with the IEEE 754-2008 standard. This paper presents the results of using our units as part of a vector co-processor and the anticipated gains once the units are moved on chip with the main processor. WHY DECIMAL HARDWARE?Ten is the natural number base or radix for humans resulting in a decimal number system while a binary system is natural to computers.In his seminal paper [1] in 1959, Buchholz concludes that "a combination of binary and decimal arithmetic in a single computer provides a high-performance tool for many diverse applications. It may be noted that the conclusion might not be the same for computers with a restricted range of functions or with performance goals limited in the interest of economy; the difference between binary and decimal operation might well be considered too small to justify incorporating both. The conclusion does appear valid for high-performance computers regardless of whether they are aimed primarily at scientific computing, business data processing, or realtime control."Due to the limited capacities of the first integrated circuits in the 1960s and later years, most machines adopted the use of dedicated circuits for binary numbers and dropped decimal numbers. With the much higher capabilities of current processors and the large increase in financial and human oriented applications over the Internet, decimal is regaining its due place. The largest change in the recent revision of the IEEE standard for floating point arithmetic [2] is the introduction of the The project "Promoting Egypt as the first decimal Arithmetic Intellectual property cores provider for financial applications in the world" (grant number C2/S1/163) is funded by the RDI Programme through the EU-Egypt Innovation Fund (EEIF). The RDI Programme is a programme of the Ministry of Higher Education and Scientific Research funded by the European Union. decimal floating point formats and the associated operations.Simple decimal fractions such as 1/10 which might represent a tax amount or a sales discount yield an infinitely recurring number if converted to a binary representation. Hence, a binary number system with a finite number of bits cannot accurately represent such fractions. When an approximated representation is used in a series of computations, the final result may deviate from the correct result expected by a human and required by the law [3], [4]. One study [5] shows that in a large billing application such an error may be up to $5 million per year.Banking, billing, and other financial applications use decimal extensively. Such applications may rely on a low-level decimal software library or use dedicated hardware circuits to perform the basic decimal arithmetic op...

show abstract

Three engines to solve verification constraints of decimal Floating-Point operation

Cited by 11 publications

References 11 publications

Binary floating point verification using random test vector generation based on SV constraints

Binary floating point verification using random test vector generation based on SV constraints

Decimal Floating Point Number System

Decimal Floating Point for future processors

Contact Info

Product

Resources

About