In the integrated circuit industry, aluminum-based interconnects and oxide interlayer dielectrics have been replaced with copper interconnects in a dual inlaid architecture and with low-K dielectrics. Inlaid Cu lines offer higher conductivity, improved electromigration performance and a reduced cost of manufacturing. In this manuscript, the current challenges with integrating Cu in high-performance integrated circuits are detailed. As technologies scale, the many steps in the integrated process flow cannot be viewed as independent. The interactions between process steps (module interactions) that must be considered will be discussed. The development of a reliable and manufacturable technology requires a fundamental understanding of these interactions. A process-oriented finite element model (FEM) will be presented to capture the effect of individual process steps on the stress evolution during processing. Finally, the future trends for Cu interconnect will be suggested.