Three-Dimensional Network-on-Chip Architecture

Xie, Yuan; Narayanan, Vijaykrishnan; Das, Chita R.

doi:10.1007/978-1-4419-0784-4_8

Cited by 11 publications

(3 citation statements)

References 26 publications

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“…24 to estimate the area of our architecture and their e±ciencies. As shown in Table 2 area e±ciency with values of 19.7%, 13.2% and 6.6% with heterogeneous architectures of 25%, 50% and 75% of 3D routers is calculated respectively.…”

Section: Area Analysismentioning

confidence: 99%

Heterogeneous 3d Network-on-Chip Architectures: Area and Power Aware Design Techniques

Agyeman

Ahmadinia

Shahrabi

2013

J CIRCUIT SYST COMP

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Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip°oorplan compared to a 2D router. Hence, more e±cient architectures should be designed. In this paper, we propose area e±cient and low power 3D heterogeneous NoC architectures, which combines both the power and performance bene¯ts of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area e±ciency of up to 61% and 19.7%, respectively.

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Section: Area Analysismentioning

confidence: 99%

Heterogeneous 3d Network-on-Chip Architectures: Area and Power Aware Design Techniques

Agyeman

Ahmadinia

Shahrabi

2013

J CIRCUIT SYST COMP

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“…Through-silicon-via (TSV) based three-dimensional (3D) integration is a promising design for interconnect-centric circuits. [1][2][3][4] One of the most important benefits of the 3D architecture over a conventional two-dimensional (2D) system is the reduction in global interconnects and total wire length, thereby providing lower cost, smaller form factor, and higher performance. The signal integrity (SI) is expected to be a major concern for 3D integrated circuits (ICs) due to the high frequency loss and the electromagnetic radiation in such a tiny 3D space.…”

Section: Introductionmentioning

confidence: 99%

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Qian¹,

Zhu²,

Xia³

et al. 2014

Chinese Phys. B

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“…Besides, some works have focused on developing 3D NoC architectures [49] and as we have seen in section 3, NoC tools developers have also anticipated these advancements by proposing tools that are dedicated for 3D NoC design and simulation [30]. However, other studies proposed different approach by adding the NoC concept to the bus one and so, keeping some data transfer to classical buses.…”

Section: G Other Available Noc Toolsmentioning

confidence: 99%

A Survey of Network-On-Chip Tools

Achballah¹,

Saoud²

2013

IJACSA

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Abstract-Nowadays System-On-Chips (SoCs) have evolved considerably in term of performances, reliability and integration capacity. The last advantage has induced the growth of the number of cores or Intellectual Properties (IPs) in a same chip. Unfortunately, this important number of IPs has caused a new issue which is the intra-communication between the elements of a same chip. To resolve this problem, a new paradigm has been introduced which is the Network-On-Chip (NoC). Since the introduction of the NoC paradigm in the last decade, new methodologies and approaches have been presented by research community and many of them have been adopted by industrials. The literature contains many relevant studies and surveys discussing NoC proposals and contributions. However, few of them have discussed or proposed a comparative study of NoC tools. The objective of this work is to establish a reliable survey about available design, simulation or implementation NoC tools. We collected an important amount of information and characteristics about NoC dedicated tools that we will present throughout this survey. This study is built around a respectable amount of references and we hope it will help scientists.

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Three-Dimensional Network-on-Chip Architecture

Cited by 11 publications

References 26 publications

Heterogeneous 3d Network-on-Chip Architectures: Area and Power Aware Design Techniques

Heterogeneous 3d Network-on-Chip Architectures: Area and Power Aware Design Techniques

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

A Survey of Network-On-Chip Tools

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