Three-Dimensional Nanoscale Flexible Memristor Networks with Ultralow Power for Information Transmission and Processing Application

Wang, Tianyu; Meng, Jialin; Rao, Mingyi; He, Zhenyu; Chen, Lin; Zhu, Hao; Sun, Qizhen; Ding, Shi‐Jin; Bao, Wenzhong; Zhou, Peng; Zhang, David Wei

doi:10.1021/acs.nanolett.9b05271

Cited by 151 publications

(133 citation statements)

References 47 publications

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“…Various amorphous (e.g., TaO x and WO x ) and complex oxide (e.g., SrTiO 3 and Pr 0.7 Ca 0.3 MnO 3 ) materials have been widely employed as the active layer for the valence change memristive synapses. [37,[71][72][73][74][75][76][98][99][100][101][102][103][104][105][106][107][108][109][110][111][112][113] The electric-field-driven soft-breakdown can generate several types of charged ions and vacancies in the active layer ( Figure 2b). [36,54,114] Inert or reactive metals have been used for both electrode terminals.…”

Section: Valence Change Synapsementioning

confidence: 99%

Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

2020

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as the thermal budget has increased rapidly in recent years, which could surpass the future revenue generated worldwide by the semiconductor industry. [4,5] Consequently, electronic miniaturization limits the sustainable growth of computing technology. The von Neumann design is a conventional computing architecture, which separates the processor and memory unit. This architecture performs a computational task through sequential procedures and has functioned a mainstay of modern computing since 1945. [6] In fact, the architecture is significantly beneficial to both hardware and software developers because each component can be improved and readily extended into a united electronic system, even without a comprehensive understanding of all the components. However, the von Neumann bottleneck generates substantial power consumption and latency during the computing operation. [2,7] This limitation results from data transmission between two functional units (processor and memory), particularly when the memory is accessed through a bus with restricted bandwidth. [2,7] Moreover, according to the International Data Corporation (IDC), global data will rapidly increase to 175 ZB (1.75 × 10 23 B) by 2025. [8] Consequently, the von Neumann bottleneck will be more detrimental under tremendous workload because it may be produced by the daily operation of the design. Recently, there has been increasing demand for intellectual computers that can efficiently process substantial global data, thereby resulting in the development of a wide range of softwareor hardware-based artificial neural networks (ANNs) aimed at achieving the computing ability of the human brain. [2,9] Softwarebased ANNs have recently exhibited remarkable capabilities, such as image recognition, [10,11] natural language processing, [12,13] and performing specific tasks, [14] some beyond the human level. However, since existing ANNs are built on conventional computing architecture, that is, the von Neumann architecture, the learning parameters stored in memory are iteratively introduced to the processor to perform a task. The bottleneck issue arising from the movement of large datasets would eventually reduce the energy and time efficiency when operating the ANN software. [2,7] To alleviate this problem, several advanced software-and hardware-based ANN approaches have been suggested. [2,7,15-17] Advanced algorithms, such as network pruning, quantization, Huffman coding, and knowledge distillation, have been Memristors have recently attracted significant interest due to their applicability as promising building blocks of neuromorphic computing and electronic systems. The dynamic reconfiguration of memristors, which is based on the history of applied electrical stimuli, can mimic both essential analog synaptic and neuronal functionalities. These can be utilized as the node and terminal devices in an artificial neural network. Consequently, the ability to understand, control, and utilize fundamental switching principles and various types of device architectures of the...

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Section: Valence Change Synapsementioning

confidence: 99%

Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

2020

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“…Many 3D CBAs are reported based on this kind of structure. [ 51,138,162,163 ] In 2015, a two‐layer 1S1R CBA with a shared BL structure was first demonstrated by Intel and Micron, in which the 1 R was made of PCM with GeSb 2 Te 4 , and 1S was made of GeSe threshold switching memristor. Adam et al fabricated 3D horizontally stacked CBAs based on Pt/Al 2 O 3 /TiO 2‐ x /TiN/Pt memristors for neuromorphic computing, which is composed of two stacked passive 10 × 10 CBAs.…”

Section: Key Requirements and Progress For Large‐scale Memristor Cbasmentioning

confidence: 99%

Hardware Implementation of Neuromorphic Computing Using Large‐Scale Memristor Crossbar Arrays

Ang

2020

Advanced Intelligent Systems

126

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Brain‐inspired neuromorphic computing is a new paradigm that holds great potential to overcome the intrinsic energy and speed issues of traditional von Neumann based computing architecture. With the ability to perform vector‐matrix multiplications and flexible tunable conductance, the memristor crossbar array (CBA) structure is one of the most promising candidates to realize neural cognitive systems. The boom in the development of memristive synapses and neurons has propelled the developments of artificial neural networks (ANNs) to emulate the highly hierarchically organized network of human brain in the past decade. To achieve this, realizing large scale, high‐density memristive CBAs is a prerequisite to constructing complex ANNs. Herein, the stringent requirements in device performance and array parameters for hardware ANNs are analyzed, and the efforts in addressing the associated challenges are discussed. Recent progress on the experimental demonstration of neuromorphic computing systems (NCSs) is presented. Recommendations for further performance optimization at the device, circuit, and algorithm levels are proposed. This Report serves as a guide for the hardware implementation of NCS based on large‐scale CBAs.

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“…For example, Wang et al prepared multiple nanoporous (NP) SiO x layers to control filament formation 29,30 , and Tour et al proposed a threedimensional NP Ta 2 O 5−x structure with graphene boasting high-density storage and low power consumption 31,32 . Obviously, a porous structure can regulate the conducting channel and enhance the device performance 33 .…”

Section: Introductionmentioning

confidence: 99%

Artificial synapses with a sponge-like double-layer porous oxide memristor

et al. 2021

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Closely following the rapid development of artificial intelligence, studies of the human brain and neurobiology are focusing on the biological mechanisms of neurons and synapses. Herein, a memory system employing a nanoporous double-layer structure for simulation of synaptic functions is described. The sponge-like double-layer porous (SLDLP) oxide stack of Pt/porous LiCoO2/porous SiO2/Si is designed as presynaptic and postsynaptic membranes. This bionic structure exhibits high ON–OFF ratios up to 108 during the stability test, and data can be maintained for 105 s despite a small read voltage of 0.5 V. Typical synaptic functions, such as nonlinear transmission characteristics, spike-timing-dependent plasticity, and learning-experience behaviors, are achieved simultaneously with this device. Based on the hydrodynamic transport mechanism of water molecules in porous sponges and the principle of water storage, the synaptic behavior of the device is discussed. The SLDLP oxide memristor is very promising due to its excellent synaptic performance and potential in neuromorphic computing.

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Three-Dimensional Nanoscale Flexible Memristor Networks with Ultralow Power for Information Transmission and Processing Application

Cited by 151 publications

References 47 publications

Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

Emerging Memristive Artificial Synapses and Neurons for Energy‐Efficient Neuromorphic Computing

Hardware Implementation of Neuromorphic Computing Using Large‐Scale Memristor Crossbar Arrays

Artificial synapses with a sponge-like double-layer porous oxide memristor

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