Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage

Guler, Abdullah; Jha, Niraj K.

doi:10.1109/tvlsi.2018.2883525

Cited by 18 publications

(7 citation statements)

References 27 publications

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“…The channel in FinFETs can be controlled from multiple sides. This eliminates the effect of the drain-induced barrier lowering, enhances the subthreshold slope, and reduces the leakage current [54]. Furthermore, the use of a lightly doped or non-doped channel reduces random doped fluctuations [55].…”

Section: Physical Structure Of Finfetmentioning

confidence: 99%

“…The 'on-current (ION) to off-current (IOFF) ratio' in SG FinFETs is better than that in IG FinFETs. Therefore, SG FinFETs are preferred for high-performance designs [54].…”

Section: Physical Structure Of Finfetmentioning

confidence: 99%

“…The values of the parameters in a 32 nm FinFET were obtained from the previous studies and the technical information from semiconductor companies. These values were then optimized for high-performance logic circuits [54].…”

Section: Physical Structure Of Finfetmentioning

confidence: 99%

“…RSNM and WSNM depend on the cell ratio (CR) and pull-up ratio (PR). CR is defined as the ratio of the size of the pull-down NMOS transistor of the inverters to the NMOS pass transistor [54]. The values of CR and PR are obtained as follows:…”

Section: Static Noise Marginmentioning

confidence: 99%

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A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

Abbasi¹,

Setoudeh²,

Tavakoli³

et al. 2022

Nanotechnology

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The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

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Section: Physical Structure Of Finfetmentioning

confidence: 99%

“…The 'on-current (ION) to off-current (IOFF) ratio' in SG FinFETs is better than that in IG FinFETs. Therefore, SG FinFETs are preferred for high-performance designs [54].…”

Section: Physical Structure Of Finfetmentioning

confidence: 99%

Section: Physical Structure Of Finfetmentioning

confidence: 99%

Section: Static Noise Marginmentioning

confidence: 99%

See 2 more Smart Citations

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

Abbasi¹,

Setoudeh²,

Tavakoli³

et al. 2022

Nanotechnology

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show abstract

“…The 8T design is introduced to separate the read operation from write in order to attain improved stability when allowing low-voltage operations [33][34]. The 8T con guration represents that, the addition of 2 FETs to a 6T cell offers a read process which won't interrupt the internal nodes of the cell.…”

Section: Finfet-8t Sram Cellmentioning

confidence: 99%

A Review On Sram Memory Design Using Finfet Technology

Lakshmi¹,

Kamaraju²

2022

Preprint

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An innovative technology named FinFET (Fin Field Effect Transistor) has been developed to offer better transistor circuit design and to balance the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices face some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents etc. However, the memory must have less power dissipation, short access time and low leakage current. The traditional design of SRAM (Static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a Nano-scaled device named FinFET is introduced for designing SRAM since it has three dimensional (3D) design of the gate. FinFET has been used to improve the overall performance, which includes efficiency, power, and area. Moreover, FinFET has been chosen as a transistor of choice because it is not affected by SCEs. In this work, we have reviewed various FinFET based SRAM cells, performance metrics and the comparison over different technologies.

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Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

Peng,

Hu,

Zheng

et al. 2024

Circuit Theory & Apps

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In an SRAM, threshold voltages of transistors decrease as the CMOS process technology scales down into the nanometer scale, which causes the leakage currents on the bit‐lines. The bit‐line leakage current slows reading operations or even causes reading errors. In this paper, we proposed a new scheme called RTB, which is combined with a four‐input low‐offset sense amplifier with threshold voltage consideration to solve the problem caused by bit‐line leakage current. This scheme adopts 8T cells and two pairs of bit‐lines connected to a four‐input sense amplifier to balance the bit‐line leakage current in real‐time. In this way, the maximum tolerable bit‐line leakage current can be effectively increased and the reading operation can be accelerated. Simulations in the 55 nm CMOS process design kits under different process corners, temperatures, and voltages show that the proposed scheme can increase the maximum tolerable leakage to more than 300 μA.

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Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage

Cited by 18 publications

References 27 publications

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

A Review On Sram Memory Design Using Finfet Technology

Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

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