Three-Dimensional Integration of Fully Depleted Silicon-on-Insulator Transistor Substrates for CMOS Image Sensors Using Au/SiO₂ Hybrid Bonding and XeF₂ Etching

Abstract

We have investigated a pixel-parallel signal processing CMOS image sensor for future TV broadcast equipment. The device has a three-dimensional structure containing functional layers made up of components such as photodiodes and signal processors formed on fully depleted silicon-on-insulator transistor substrates connected with vertical interconnections formed for each pixel. To demonstrate the effectiveness of this approach, a test chip is experimentally constructed using Au/SiO2 hybrid bonding technology. Mechanical grinding and XeF2 etching are utilized to remove the backside Si layer to allow light transmission to the photodiode. Due to the high bonding strength after the surface activation treatment, the Si layer thickness could be reduced to 40 µm without chipping. The proposed approach is highly promising for the fabrication of three-dimensional integrated image sensors.

Three-Layered Stacking Process by Au/SiO2Hybrid Bonding for 3D Structured Image Sensors

“…To overcome this problem, we developed a 3D structured CMOS image sensor, as shown in Fig. 1 (7)(8)(9)(10). This sensor can process signals pixelwise in parallel as a means to simultaneously increase the pixel count and frame rate.…”