Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study

Abstract

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

“…Firstly, the bump structure is modeled, and current density boundary conditions and temperature boundary conditions are set based on the current equation and heat transfer equation. Tian established an equivalent model of the vertical stacking structure of fan-out wafer-level packages [50]; the simulation loaded the model with an electrical-thermal environment using COMSOL. The model and results are shown in Figure 11.…”