Three-Dimensional Error Correction Schemes for Holographic Data Storage

Hwang, Euiseok; Yoon, Pilsang; Park, Joo Youn; Park, Jongyong; Nam, Ha-eun

doi:10.1143/jjap.44.3529

Cited by 20 publications

(12 citation statements)

References 7 publications

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“…1) To manage these two problems, many kinds of equalizers, [3][4][5][6][7][8] modulation codes, [9][10][11][12][13][14] and error correcting codes were developed. [15][16][17] To compensate for data distortion, we propose two types of 2D iterative decoding (ID) schemes. One is the ID scheme using a single parity bit (ID-SPB).…”

Section: Introductionmentioning

confidence: 99%

Two-Dimensional Iterative Decoding Schemes for Holographic Data Storage Systems

Kim

Kong

Choi³

2012

Jpn. J. Appl. Phys.

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Two iterative decoding (ID) schemes, which are the ID using a single parity bit (ID-SPB) and ID using a modulation code (ID-MC), are proposed for holographic data storage systems. In the ID-SPB, a single two-dimensional parity bit is employed to conduct ID, whereas in the ID-MC, the inherent constraint of the modulation code is utilized to conduct ID. In both schemes, a data page is iteratively decoded by exchanging extrinsic information between the horizontal and vertical data bits in the page. In particular, in the ID-SPB, by adding more parity bits to each row and column of the interleaved page, we can conduct the ID within a page as well as between the original and interleaved pages. Thus, additional performance gain can be achieved in the ID-SPB. On the other hand, the ID-MC has a performance gain without loss of data rate since parity bits are not required for ID. The simulation results show that the proposed ID-SPB and ID-MC have about 2-4 and 1-2 dB performance gains in terms of bit error rate compared with the system without ID, respectively. #

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Section: Introductionmentioning

confidence: 99%

Two-Dimensional Iterative Decoding Schemes for Holographic Data Storage Systems

Kim

Kong

Choi³

2012

Jpn. J. Appl. Phys.

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“…Accordingly, RS ECC should be applied in three dimensions. For example, E. S. Hwang et al proposed a three-dimensional error correcting scheme (RS Volumetric Code -RSVC) which attained better error control performance than RS ECC and RSPC [8,10] . However, only general multi-dimensional interleaving methods [11] were incorporated in their threedimensional error correcting scheme, and no specific design was made to the error patterns in the HDS channel.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional error correcting with matched interleaving for holographic data storage

Cao

et al. 2011

SPIE Proceedings

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For applying to various error patterns, including random errors, burst errors, and inhomogeneously distributed errors, in the holographic data storage (HDS) channel, a three-dimensional error correcting with matched interleaving (3DEC-MI) scheme is proposed in this paper. The 3DEC-MI scheme combines the advantages of the three-dimensional error correcting scheme and the matched interleaving scheme, makes full use of the priori knowledge of the error patterns in the HDS channel, distributes errors more uniformly, and decodes data iteratively in three dimensions. It is able to eliminate the influences of non-uniform distribution of errors within a page and across pages, overcome the effects of burst errors, correct random errors, and effectively reduce the symbol error rate (SER) of the HDS channel.

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“…Therefore, an effective signal processing algorithm has been proposed for reliable data readout over noisy HDDS channels. [3][4][5][6][7][8] Appropriate channel coding and decoding schemes are implemented with a field-programmable gate array (FPGA) chip for fast data processing. The hardware channel board is designed to demonstrate real-time recording and reading of the DEPROTO-III, which is the prototype HDDS developed at Daewoo.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Hardware Channel Board for Holographic Data Storage

Yoon

Kim

Park

et al. 2009

jjap

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A channel board has been designed, manufactured, and used for real-time recording and reading processes. The channel coding and decoding algorithms were implemented on Xilinx field-programmable gate array (FPGA) devices. For fast data transmission between the channel board and personal computer (PC), a universal serial bus (USB) 2.0 interface is installed in the channel board. The firmware and device driver for USB interface achieved a transfer rate of 34 Mbyte/s. A holographic data storage system records a video stream, which was successfully retrieved and reconstructed without error. #

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Three-Dimensional Error Correction Schemes for Holographic Data Storage

Cited by 20 publications

References 7 publications

Two-Dimensional Iterative Decoding Schemes for Holographic Data Storage Systems

Two-Dimensional Iterative Decoding Schemes for Holographic Data Storage Systems

Three-dimensional error correcting with matched interleaving for holographic data storage

Design and Implementation of a Hardware Channel Board for Holographic Data Storage

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