Three-dimensional discrete wavelet transform architectures

Weeks, Michael; Bayoumi, Magdy

doi:10.1109/tsp.2002.800402

Cited by 47 publications

(16 citation statements)

References 32 publications

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“…It is found that, the proposed design has less memory requirement, High throughput, less computation time and minimal latency compared to [19], [20], [22], and [24]. Though the proposed 3-D DWT architecture has small disadvantage in area and frequency, when compared to [22], the proposed one has a great advantage in remaining all aspects.…”

Section: A Comparisonmentioning

confidence: 93%

High performance VLSI architecture for 3-D discrete wavelet transform

Srinivasarao

Chakrabarti

2016

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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This paper presents a memory efficient, high throughput parallel lifting based running three dimensional discrete wavelet transform (3-D DWT) architecture. 3-D DWT is constructed by combining the two spatial and four temporal processors. Spatial processor (SP) apply the two dimensional DWT on a frame, using lifting based 9/7 filter bank through the row rocessor (RP) in row direction and then apply in the colum direction through column processor (CP). To reduce the temporal memory and the latency, the temporal processor (TP) has been designed with lifting based 1-D Haar wavelet filter. The proposed architecture replaced the multiplications by pipeline shift-add operations to reduce the CPD. Two spatial processors works simultaneously on two adjacent frames and provide 2-D DWT coefficients as inputs to the temporal processors. TPs apply the one dimensional DWT in temporal direction and provide eight 3-D DWT coefficients per clock (throughput). Higher throughput reduces the computing cycles per frame and enable the lower power consumption. Implementation results shows that the proposed architecture has the advantage in reduced memory, low power consumption, low latency, and high throughput over the existing designs. The RTL of the proposed architecture is described using verilog and synthesized using 90-nm technology CMOS standard cell library and results show that it consumes 43.42 mW power and occupies an area equivalent to 231.45 K equivalent gate at frequency of 200 MHz. The proposed architecture has also been synthesised for the Xilinx zynq 7020 series field programmable gate array (FPGA). Index TermsIndex Terms : discrete wavelet transform, 3-D DWT, lifting based DWT, VLSI Architecture, flipping structure, strip-based scanning.

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Section: A Comparisonmentioning

confidence: 93%

High performance VLSI architecture for 3-D discrete wavelet transform

Srinivasarao

Chakrabarti

2016

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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“…The three -dimensional DWT can be considered as a combination of three 1-D DWT in the X, Y and Z directions [3]. First, the process transforms the data in the X-direction.…”

Section: Three -Dimensional Discrete Wavelet Transformmentioning

confidence: 99%

“…This scheme consists of three major stages: (i) Split (ii) Predict (iii) update. Lifting-based DWT architectures can be constructed by combining the above mentioned three basic lifting elements, split, predict and update [3,4]. The input image coefficients are split into the odd and even coefficients in the split stage.…”

Section: Lifting Based Discrete Wavelet Transformmentioning

confidence: 99%

VLSI Architectures for Lifting Based Discrete Wavelet Transform – A Survey

Kalaiarasi¹,

Vigneswaran²

2016

IJEECS

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“…This is the main reason for use of DWT in JPEG2000 [7]. For video coding, both 3D and 2D wavelet decompositions with motion estimation are used [5,8,9]. The main problem of these methods is boundary effects.…”

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confidence: 99%

Hybrid spatial scalable video codec for HDTV video images

Seirafian

Naderpour

Ghanaati

et al. 2011

2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE)

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In this paper, a scalable hybrid video codec has been developed for HDTV video signals. The intra frame pictures are coded based on wavelet transform and inter frame pictures are coded with a standard MPEG-2 codec.By scalable coding of HDTV, channels transmit with various speeds and capacities; In addition, receivers can work at different resolutions. Base layer and enhancement layer of the frame picture are coded with same codec. This paper compares scalable hybrid coding with scalable MPEG-2 codec and scalable DWT2 method for HDTV video signals. It is showed that the quality of intra frame improves by using the proposed codec in comparison with two other methods. By this improvement, the quality of sequence increases.

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Three-dimensional discrete wavelet transform architectures

Cited by 47 publications

References 32 publications

High performance VLSI architecture for 3-D discrete wavelet transform

High performance VLSI architecture for 3-D discrete wavelet transform

VLSI Architectures for Lifting Based Discrete Wavelet Transform – A Survey

Hybrid spatial scalable video codec for HDTV video images

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